Transaction Flow

The general flow of an I2C transaction is:

Bus is idle with SDA = HIGH and SCL = HIGH.
Controller generates START.
Controller sends target address and read/write bit.
Addressed target responds with ACK.
Data bytes are transferred.
Each byte is followed by ACK or NACK.
Controller generates STOP or repeated START.

I2C bit transfer rule

In I2C, data must remain stable when SCL is HIGH. SDA can change when SCL is LOW.

This rule helps all devices sample the data at the correct time.

Address phase

The first byte after START contains the target address and read/write bit. All target devices monitor the bus, but only the addressed target responds.

For 7-bit addressing:

The address phase uses the 7-bit address, followed by the read/write bit and the receiver’s ACK/NACK response.

If no device responds, SDA remains HIGH during the ACK clock, which is interpreted as NACK.

Data Phase

After the address is acknowledged, data transfer begins.

During a write operation, the controller drives SDA for each data bit and the target sends ACK/NACK after each byte.

During a read operation, the target drives SDA for each data bit and the controller sends ACK/NACK after each byte.

ACK/NACK handling

ACK/NACK controls byte-level handshaking.

Common NACK cases include:

No target exists at the requested address.
Target is busy.
Target does not support the requested operation.
Receiver cannot accept more data.
Controller has completed a read transfer.

I2C Protocol