UART Operations

Transmitter Operation

The transmitter converts a parallel data word into a serial frame.

Basic transmit sequence:

Wait in idle state with TX = 1.
Accept a data word when the transmitter is not busy.
Drive the start bit, TX = 0, for one bit time.
Shift data bits out, LSB first.
Optionally transmit parity.
Drive stop bit(s), TX = 1.
Return to idle or start the next frame.

Receiver Operation

The receiver watches the serial input and reconstructs the frame.

Basic receive sequence:

Wait for idle/high line.
Detect a high-to-low transition that may be a start bit.
Confirm the start bit near its middle.
Sample each data bit near the middle of its bit time.
Check optional parity.
Check stop bit.
Deliver received data and status flags.

Oversampling

Many UART receivers oversample the input, commonly at a multiple of the baud rate, to detect the start edge and choose a stable middle-of-bit sample point. For example, a receiver may use a 16x internal sampling clock, detect the start transition, then sample near the midpoint of the start bit and later bits.

Oversampling is a common implementation technique. It is not a requirement of the abstract UART frame format.

Parity

Parity adds one optional bit after the data bits.

Mode	Meaning
None	No parity bit
Even	Total number of 1 bits across data plus parity should be even
Odd	Total number of 1 bits across data plus parity should be odd

Example for data 8’b0101_0011:

Data ones = 4
Even parity bit = 0, because total ones already even
Odd parity bit  = 1, because total ones must become odd

Parity can detect many single-bit errors, but it is not a strong integrity mechanism. It cannot detect all multi-bit errors and does not correct data.

UART Error Conditions

Error	Generic meaning	Typical cause
Framing error	Stop bit was not observed as expected	Baud mismatch, noise, wrong frame config, line stuck low
Parity error	Received parity does not match data	Noise, wrong parity setting, bit corruption
Overrun error	New data arrived before previous data was consumed	Software too slow, insufficient buffering
Break-like condition	Line held low longer than a normal character frame	Deliberate break signaling, fault, wiring issue

Note: Exact status flag names and clearing behavior are implementation-specific. A generic tutorial should explain the concept without assuming a register model.

UART Protocol