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Verilog
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RAL Model
Transaction Level Modeling (TLM)
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Verilog
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Verilog Codes
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System Verilog
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Functional Coverage
SystemVerilog Assertions
UVM
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RAL Model
Transaction Level Modeling (TLM)
Interview Questions
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Verilog Interview Questions
SystemVerilog Interview Questions
UVM Interview Questions
ASIC Flows
Blogs
Resources
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Verilog Codes
Content
Index
Half Adder
Full Adder
Half Subtractor
Full Subtractor
Ripple Carry Adder
4-bit Adder Subtractor
Carry Look Ahead Adder
Binary to Gray Code Converter
Gray to Binary Code Converter
Multiplexer
2:1 Multiplexer
4:1 Multiplexer
4:1 MUX using 2:1 MUX
3:1 Multiplexer
Demultiplexer
1:2 Demultiplexer
1:4 Demultiplexer
1:4 DEMUX using 1:2 DEMUX
Encoder
Binary Encoder
Priority Encoder
Decoder
Comparator
Array Multiplier
Booth’s Multiplier
Wallace Tree Multiplier
DFF with Asynchronous Reset
DFF with Synchronous Reset
SR Flip Flop
JK Flip Flop
T Flip Flop
Universal Shift Register
Linear feedback shift register (LFSR)
Asynchronous Counter
Synchronous Counter
Mealy Sequence Detector
Moore Sequence Detector
Synchronous FIFO
Asynchronous FIFO
