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Assume statement
The assume statement allows properties to be considered as assumptions for dynamic simulation tools and formal analysis.
For a simulation environment, assume the statement is the same as an assert statement that checks assumed property and reports success or failure.
For formal analysis, an assumed property can be considered as a hypothesis to prove asserted property without having any bound.
Syntax:
<assume_label>: assume <property>
Assume stememt example
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assume_a2: assume property (prop);
property prop;
@(posedge clk) req1 ##2 req2;
endproperty
//is same as
assume_a1: assume property (@(posedge clk) req1 ##2 req2);
Cover statement
The cover statement is used to gather coverage information for the specified sequences or properties.
Syntax:
cover property (<sequence>) <statement_or_null>
The result of the coverage statement shall include
For a property |
For a sequence |
The number of times property attempted, failed, or succeeded (even due to vacuity which is applicable only for implication operator). |
The number of times a sequence attempted and matched. |
For a successful property, statement_or_null is executed every time. |
For every match, statement_or_null gets executed. |
Cover statement example
cover_prop: cover property (prop) $display("The prop property is hit");
property prop;
req1 |=> req2
endproperty
SystemVerilog Assertions