Universal Verification Methodology

UVM Introduction

The Accellera Universal Verification Methodology (UVM) is a standard verification methodology that includes a set of class libraries for the development of a verification environment. UVM is based on Open Verification Methodology (OVM) and Verification Methodology Manual (VVM).

The UVM API (Application Programming Interface) provides standardization for integration, creation of verification components. The API also scales from block-level to system-level verification environment. 

Advantages of UVM based testbench

  1. UVM methodology provides scalable, reusable, and interoperable testbench development.
  2. To have uniformity in the testbench structure across the verification team, UVM provides guidelines for testbench development.
  3. UVM provides base class libraries so that users can inherit them to use inbuilt functionality.
  4. The driver-sequencer communication mechanism is an inbuilt mechanism in UVM that reduces verification efforts for the connection.
  5. UVM also provides verbosity to control message displays.