Learn More

Contents hide
1 Verilog Interview Questions with Answers
Contents hide
1 Verilog Interview Questions with Answers

Basic Level Questions

1. Difference between blocking and non-blocking assignments

Blocking Assignments: The blocking assignment statements are executed sequentially by evaluating the RHS operand and finishes the assignment to LHS operand without any interruption from another Verilog statement. Hence, it blocks other assignments until the current assignment completes and is named a “blocking assignment”.
Ex: a = 5;
Non-Blocking Assignments: The non-blocking assignment statement starts its execution by evaluating the RHS operand at the beginning of a time slot and schedules its update to the LHS operand at the end of a time slot. Other Verilog statements can be executed between the evaluation of the RHS operand and the update of the LHS operand. As it does not block other Verilog statement assignments, it is called a non-blocking assignment.
Ex: a <= 5;

2. Difference between task and function

3. Difference between wire and reg

Net types: 

  1. The net (wire, tri) is used for physical connection between structural elements.
  2. Value is assigned by a continuous assignment or a gate output or port of a module.
  3. It can not store any value. The values can be either read or assigned.
  4. Default value – z

Register type: 

  1. The register (reg, integer, time, real, real-time) represents an abstract data storage element and they are not the physical registers.
  2. Value is assigned only within an initial or an always statement.
  3. It can store the value. 
  4. Default value – x

4. What is generate block in Verilog and its usage?

5. Difference between while and do-while loop

Refer: Difference between while and do while loop

Also, refer example to understand more.

6. What is an automatic keyword in the task?

The automatic keyword specifies the variable’s scope within a task i.e. memory is allocated for the variables in the task and deallocated once the task completes execution. All variables declared in an automatic task are automatic variables unless they are specifically mentioned as a static variable.

Refer an example mentioned under section: Static and Automatic Tasks

9. Explain the difference between a static and automatic function with example.

10. Difference between $stop and $finish.

$stop suspends the simulation and puts a simulator in an interactive mode.

$finish exits the simulation.

11. Difference between $random and $urandom

Both generate 32-bit pseudorandom numbers, but $random generates signed whereas $urandom generates unsigned numbers.

Intermediate level questions

1. What is the default value of wire and reg?

The default value of the wire or net is z

The default value of the reg is x

2. Explain Regular delay control, Intra-assignment delay control

Regular delay control:

The regular delay control delays the execution of the entire statement by a specified value. The non-zero delay is specified at the LHS of the procedural statement.

Example: #5 data = i_value;

In this case, the result signal value will be updated after 5-time units for change happen in its input.

Intra-assignment delay: 

Intra-assignment delay control delays computed value assignment by a specified value. The RHS operand expression is evaluated at the current simulation time and assigned to the LHS operand after a specified delay value.

Example: data = #5 i_value;

3. Difference between full and parallel case

Full Case:

In a full case statement, case statements cover every possible input value is explicitly specified and there are no unspecified or “don’t care” conditions.


case (input)
  3'b000: ………
  3'b001: ………
  3'b010: ………
  3'b011: ………
  3'b100: ………
  3'b101: ………
  3'b110: ………
  3'b110: ………
  default: // any other input case which is not covered

Parallel Case:

In a parallel case statement, multiple case items can match the input value simultaneously and the corresponding behaviors for that will be executed in parallel.


case (input)
  4'b0?: ………
  4'b1?: ………
  // other cases
  default: // any other input case which is not covered

4. Difference between casex and casez

5. What is synchronous and asynchronous reset? Can you explain using DFF and write their Verilog code?

In asynchronous reset, a flip flop gets reset as soon as the ‘reset’ signal is asserted. Thus, in Verilog implementation, the ‘reset’ signal has to be written in the sensitivity list of always block.

Refer for code and block diagram: asynchronous reset

In synchronous reset, a flip flop gets reset at the active ‘clock’ edge when the ‘reset’ signal is asserted.

Thus, in Verilog implementation, the ‘reset’ signal must not be written in the sensitivity list of always block.

Refer for code and block diagram: synchronous reset

6. What is #0 in Verilog and its usage?

Zero delay control is used to control execution order when multiple procedural blocks try to update values of the same variable. Both always and initial blocks execution order is non-deterministic as they start evaluation at the same simulation time. The statement having zero control delay executes last, thus it avoids race conditions.


reg [2:0] data;
initial begin 
  data = 2;
initial begin 
  #0 data = 3;

Without zero delay control, the ‘data’ variable may have a value of either 2 or 3 due to race conditions. Having zero delay statement as specified in the above code guarantees the outcome to be 3. However, it is not recommended to assign value to the variable at the same simulation time.

7. How to generate two different clocks in testbench?

module tb;
  bit clk1, clk2; 
  initial forever #5ns clk1 = ~clk1;
  initial forever #4ns clk2 = ~clk2;

8. Design overlapping and non-overlapping FSM for sequence detector 1010.

9. Write a Verilog code for D-Latch.

The latch has two inputs ‘data (D)’ and ‘clock (clk)’

One output data (Q)

If clk = 1, then data passes to the output Q

If clk = 0, then data is not passed to the output Q

module d_latch (input d, en, rst_n, output reg q);
  always @(en or rst_n or d) begin
    if(!rst_n) begin
      q <= 0;
    else begin
      if(en) q <= d;

10. How can you override the existing parameter value?

11. What is Synthesis?

The process of converting hardware description language like Verilog code into the equivalent netlist design that has flip-flops, logic gates, and required digital circuit components.

12. Write an RTL code to generate 60% duty cycle clock.

`define CLK_PERIOD 10ns
module clk_gen;
  realtime on_t = `CLK_PERIOD * 0.6;
  realtime off_t = `CLK_PERIOD * 0.4;
  bit clk;
  always begin
    #on_t clk = 0;
    #off_t clk = 1;
  initial begin
    clk = 1;
    #50 $finish;
  initial begin
    // Dump waves

13. Write an RTL code to generate 100MHz clock.

To generate clock frequency, time period needs to be calculated.

Time Period = 1/frequency = 1/100MHz = 10ns

With a 50% duty cycle, clock has to flip a bit after every 5ns.

module clk_gen;
  reg clk;
  always #5 clk = ~clk;

14. Difference between `define and `include.

`define is a compiler directive that substitutes itself in the code with a defined context. In simple words, wherever macro is used, it is replaced with macro context and gives compilation error in case of misuse.

The `include is also a compiler directive is used to include another filename. The double quote “<file_name>” is used in the `include directive. It is widely used to include library files, and common code instead of pasting the same code repeatedly.

Refer to examples: compiler directives

15. What is force and release in Verilog?

17. What will be output of the following code?

always@(clock) begin
  a = 0;
  a <= 1;

In order to answer this question, you should understand what is scheduling semantics in Verilog.

In brief, A single time cycle or slot is divided into various regions and that helps to schedule the events. The scheduling an event terminology describes keeping all such events in an event queue and processing them in the correct order. In this case, there are 3 events scheduled in an event queue.

  1. Active event – blocking statement “a = 0”.
  2. A non-blocking event – non-blocking statement “a <= 1”
  3. Monitor event – “$display(a)”.

$display acknowledges and displays what value is being calculated as an active region. Also, a non-blocking event computes (not assigned to RHS ‘a’ variable) LHS during the active region. Thus, it will pick up the value calculated by the statement “a = 0”. But in the next clock cycle, the value of a = 1.

Difficult level questions

1. Why always block is not used inside a program block?

The program block is generally used to develop a test case that initiates a stimulus and then it should end. But the ‘always’ block does not have any provision to end by itself. Thus, we can not have a program block. Even if you try to do so, a compilation error is expected.

For a need basic, we can use the ‘forever’ loop as a work-around with a ‘break’ statement to terminate the loop as per requirement.

2. What is FIFO? What are underflow and overflow conditions in FIFO? Write Verilog code for the design.

FIFO stands for first in first out which means that the first element enters into the buffer and comes out first.

Underflow:  When an attempt is made to read data from an empty FIFO, it is called an underflow. The design should have an ‘empty’ flag to avoid getting invalid values

Overflow: When an attempt is made to write data into the already full FIFO, it is called an overflow. The design should have a ‘full’ flag to avoid losing the data sent from the previous module.

Refer verilog implementation of FIFO to explain working read and write pointers to determine underflow and overflow conditions: Synchronous FIFO

3. What are all different applications of FIFO?

Buffers: To hold data immediately till we get acknowledgment whether previous data is processed by a design or not.

Clock domain crossing: To exchange data between two systems that work on different clock frequencies

Ordering requirement in design: FIFO helps to process the data in the required order which ensures data is not overridden mistakenly. This is very helpful in microprocessors, and GPU designs, etc.

Pipeline Stages: FIFO makes sure the data flows in different pipeline stages to process multiple instructions concurrently.

4. What will happen if there is no else part in if-else?

In such a case, the missing ‘else’ (i.e. valid = 0 in the below case) infers to latch in synthesis.


always@(*) begin
  if(en) begin
    data <= 8‘hFF;

5. Swap register content with and without using an extra register.

Without using an extra register:

always @(posedge clk) begin
  m <= n;
  n <= m;

Using an extra register (in case the interviewer asks):

Here, temp is an extra register used.

always @(posedge clk) begin
  temp = n;
  n = m;
  m = temp;

6. What is infer latch means? How can you avoid it?

Infer latch means creating a feedback loop from the output back to the input due to missing if-else condition or missing ‘default’ in a ‘case’ statement. 

Infer latch indicates that the design might not be implemented as intended and can result in race conditions and timing issues.

How to avoid it?

  1. Always use all branches in the ‘if’ and ‘case’ statements.
  2. Use default in the ‘case’ statement.
  3. Have a proper code review.
  4. Use lint tools, and logical-equivalence-check tools

7. How can you define strength in Verilog

8. What is parameter overriding in Verilog?

Verilog parameter is used to pass a constant to the module when it is instantiated. The parameter value can not be changed at run time.

There are two ways to override the parameters in Verilog

  1. During module instantiation
module param_example #(parameter DATA_WIDTH = 8, ID_WIDTH = 32) (data, id);
param_example #(4, 16) p2(.data(3), .id(2));

       2. Using defparam

defparam p4.DATA_WIDTH = 10;
defparam p4.ID_WIDTH = 16;

9. Write a Verilog code for 5:1 MUX

5:1 MUX selects one out of 5 signals based on 3-bit select input and forwards it to single-bit output.

module mux_5_1 (input [4:0] i_data, [2:0] sel, output reg out);
  always@(*) begin
      5'h0: out = i_data[0];
      5'h1: out = i_data[1];
      5'h2: out = i_data[2];
      5'h3: out = i_data[3];
      default: out = i_data[4];

10. Can you talk about the Verilog event scheduler?

The Verilog scheduling semantics is used to describe the Verilog language element’s behavior and their interaction with each other. This interaction is described for event execution and its scheduling. Verilog is like a parallel programming language in terms of blocks or process executions. Hence, the user should know the guaranteed or indeterminate execution order while using it.

For a detailed explanation, refer Scheduling Semantics

11. Difference between dual port ram and FIFO.

Dual Port RAM



Concurrent access to different memory access for read and write operations without causing interference. 

FIFO stands for first in first out which means that the first element enters into the buffer and comes out first. 


It has two separate ports for read/write simultaneous access.

It has one end for writing into the FIFO and another end for reading.

Control signals

The operation takes care using signals like Read/Write enable signals.

The operation takes care using read/write pointers.


Useful where simultaneous access to the memory is required like shared memory among processors, GPU, etc

Useful as a buffer to exchange data between two systems that work on different clock frequencies.

12. What is `timescale? What does `timescale 1 ns/ 1 ps in a Verilog code?

It is a ‘compile directive’ and is used for the measurement of simulation time and delay. Refer: `timescale

13. What will be the output of m, n, o if c is the clock?

logic m = c;
reg n = c;
wire o = c;

Since clock c needs to be generated, it has to be of reg type. If we do direct assignment as above, then m and n will have default values as x and wire o will be the same as how clock is driven.

But if we do declaration and assignment in the ‘always’ block then m and n can be driven same as a clock, but ‘o = c’ assignment can not be possible inside ‘always’ block as the ‘o’ variable is a wire type.