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Compiler directives in Verilog

The compiler directives are similar to C language preprocessor directives that may be used to specify certain information and ask the compiler to process it. The character ` is used prior to the specific keyword. Its declaration can be put outside of the module and its scope may not be limited to a single module.

Syntax: `<keyword>

Compiler directives

Description

`define

To define text macros. (Similar to #define in C language)

`include

To include entire content from another Verilog file into the existing file during compilation.  (Similar to #include in C language).

`ifdef…`endif

`ifdef..`else..`endif

Conditional compiler directives that behave as if..else conditional statements.

`timescale

To specify time units and precision for the module

‘ifdef, ‘else, and ‘endif Directives

module dut(
  input i1, i2,
  output out
);
  `ifdef AND_OP
    assign out = i1 & i2;
  `else
    assign out = i1 | i2;
  `endif
endmodule

Testbench:

module tb;
  reg i1, i2;
  wire out;
  
  dut and_or(i1, i2, out);
  initial begin
    `ifdef AND_OP
      $monitor("[AND Operation] At time T = %0t: i1 = %b, i2 = %b, out = %b", $time, i1, i2, out);
    `else
      $monitor("[OR Operation] At time T = %0t: i1 = %b, i2 = %b, out = %b", $time, i1, i2, out);
    `endif
    i1 = 0; i2 = 0;
    #1;
    i1 = 0; i2 = 1;
    #1;
    i1 = 1; i2 = 0;
    #1;
    i1 = 1; i2 = 1;
  end
endmodule

Output:

[AND Operation] At time T = 0: i1 = 0, i2 = 0, out = 0
[AND Operation] At time T = 1: i1 = 0, i2 = 1, out = 0
[AND Operation] At time T = 2: i1 = 1, i2 = 0, out = 0
[AND Operation] At time T = 3: i1 = 1, i2 = 1, out = 1

If the AND_OP macro is specified as a run option, a corresponding ‘AND’ operation is performed otherwise, the ‘OR’ operation is executed by default.

`timescale

Syntax:

`timescale <time_unit>/<time_precision>

time_unit: Measurement for simulation time and delay.

time_precision: Rounding the simulation time values means the simulator can at least advance by a specified value.

Examples

 `timescale 1ns/1ns

`timescale 1ns/1ns
module tb;
  initial begin
    $display ("At time T=%0t", $realtime);
    #0.45;
    $display ("At time T=%0t", $realtime);
    #0.50;
    $display ("At time T=%0t", $realtime);
    #0.55;
    $display ("At time T=%0t", $realtime);
  end
endmodule

Output:

At time T=0 
At time T=0 
At time T=1 
At time T=2

 `timescale 1ns/1ps

`timescale 1ns/1ps
module tb;
  initial begin
    $display ("At time T=%0t", $realtime);
    #0.45;
    $display ("At time T=%0t", $realtime);
    #0.50;
    $display ("At time T=%0t", $realtime);
    #0.55;
    $display ("At time T=%0t", $realtime);
  end
endmodule

Output:

At time T=0
At time T=450 
At time T=950
At time T=1500

 `timescale 10ns/1ns

`timescale 10ns/1ns
module tb;
  initial begin
    $display ("At time T=%0t", $realtime);
    #0.45;
    $display ("At time T=%0t", $realtime);
    #0.50;
    $display ("At time T=%0t", $realtime);
    #0.55;
    $display ("At time T=%0t", $realtime);
  end
endmodule

Output:

At time T=0
At time T=5
At time T=10
At time T=16

Explaination:

 `timescale 1ns/1ns: Since precision = 1ns, the simulator will advance its time if the delay value is greater or equal to 0.5ns. Thus, time advancement does not happen for 0.45ns delay.

 `timescale 1ns/1ps:  Since precision = 1ps, the simulator will advance for all the cases.

 `timescale 10ns/1ns:  Since precision = 1ns, the simulator will advance for all the cases. Here, the delay involved is multiplied with mentioned time units and then it rounds off based on precision to calculate actual simulation advancement.

Actual simulation time 

  1. (0.45*10) = 4.5ns — Rounded off to 5ns
  2. (0.50*10) = 5ns
  3. (0.55*10) = 5.5ns — Rounded off to 6ns

Note: if the timescale is not mentioned then the simulator takes default timescale values.

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