Tasks and Functions in Verilog

A function or task is a group of statements that performs some specific action. Both of them can be called at various points to perform a certain operation. They are also used to break large code into smaller pieces to make it easier to read and debug.

Functions in Verilog

A function that does not consume simulation time, returns a single value or an expression, and may or may not take arguments.

Keywords used: function and endfunction.

Syntax:

// Style 1
function <return_type> <function_name> (input <port_list>,inout <port_list>, output <port_list>);
 ...
 return <value or expression>
endfunction

// Style 2
function <return_type> <function_name> ();
  input <port_list>;
  inout <port_list>;
  output <port_list>;
  ...
  return <value or expression>
endfunction

Example:

module function_example;
  
  function compare(input int a, b);
    if(a>b)
      $display("a is greater than b");
    else if(a<b)
      $display("a is less than b");
    else 
      $display("a is equal to b");
    return 1; // Not mandatory to write
  endfunction
  
  initial begin
    compare(10,10);
    compare(5, 9);
    compare(9, 5);
  end
endmodule

Output:

a is equal to b
a is less than b
a is greater than b

Tasks in Verilog

A task that may or may not consume simulation time, returns values as output or inout argument type, and may or may not take arguments.

Keywords used: task and endtask.

Syntax:

// Style 1
task <task_name> (input <port_list>, inout <port_list>, output <port_list>);
 ...
endtask

// Style 2
task <task_name> ();
  input <port_list>;
  inout <port_list>;
  output <port_list>;
  ...
endtask

Example:

module task_example;
  
  task compare(input int a, b, output done);
    if(a>b)
      $display("a is greater than b");
    else if(a<b)
      $display("a is less than b");
    else 
      $display("a is equal to b");
    
    #10;
    done = 1;
  endtask
  
  initial begin
    bit done;
    compare(10,10, done);
    if(done) $display("comparison completed at time = %0t", $time);
    compare(5,9, done);
    if(done) $display("comparison completed at time = %0t", $time);
    compare(9,5, done);
    if(done) $display("comparison completed at time = %0t", $time);
  end
endmodule

Output:

a is equal to b
comparison completed at time = 10
a is less than b
comparison completed at time = 20
a is greater than b
comparison completed at time = 30

Similarities between function and task

Both are static in nature by default. Refer to System Verilog tasks and functions for more details.
Both support default arguments and arguments have input direction by default unless it is specified.
Multiple statements can be written without using a begin .. end block.

Difference between function and task

Function	Task
Can not contain simulation delay, so execute in the same time unit. It can not contain @, wait, negedge, and posedge time-controlled statements.	can or can not contain a simulation time delay(#), @, wait, negedge, and posedge time-controlled statements.
Can return a single value	Can return multiple values as output or inout argument. It can not return a value that a function can do.
Can not call another task	Can call another function or task