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Strength in Verilog

The strength is used to have more accurate modeling that specifies a value on a net.

The strength of a net is derived based on the strength of multiple drivers and the final strength will get the strength of the strongest driver.

Verilog provides three types of strength.

  1. Driving strength
  2. Capacitive strength
  3. High impedance

Strength type

Name of strength

Driving strength

Supply drive, strong drive, pull drive, weak drive

Capacitive strength

Large capacitive, medium capacitive, small capacitive

impedance

High impedance

Keywords used in Verilog strength

Strength level

Name of strength

keywords

0

High impedance

highz0, highz1

1

Small capacitive

small

2

Medium drive

medium

3

Weak drive

weak0, weak1

4

Large capacitive

large

5

Pull drive

pull0, pull1

6

Strong drive

strong0, strong1

7

Supply drive

supply0, supply1

Note:

  1. The default strength is the strong drive.
  2. The default strength for pullup and pulldown gates is the pull drive.
  3. The default strength for trireg is medium capacitive.
  4. The default strength for supply nets is the supply driver.
  5. A net can not be driven with a high impedance strength.
  6. The (highz1, highz0) and (highz0, highz1) strength combinations are not allowed.
  7. If a net is driven with 0 (low) and 1 (high) simultaneously, the result will be ‘x’.

Syntax:

( <strength0>, <strength1> )  
( <strength1>, <strength0> ) 
 cap_strength 

Where,
strength1 = highz1,  pull1,  strong1,  supply1, weak1
strength0 = highz0, pull0, strong0, supply0, weak0
cap_strength = large,  medium, small

strength0: When net drivers drive the value as 0, then strength is specified by strength0.

strength1:  When net drivers drive the value as 1, then strength is specified by strength1.

cap_strength:  For trireg nets, the only cap_strenth is applicable.

For example:

or (strong0, weak1) o1(out, i1, i2)

assign (weak0, strong1) out = i1 & i2;

trireg (large) tr1

Verilog strength Example

When below ‘OR’ and ‘AND’ operation drives the same output,  the final strength of the output be the strength of the strongest driver.

or (supply1, pull0) o1(out, i1, i2)

and (strong1, supply0) a1(out, i1, i2)

Input driven

Output strength

Explanation

i0 = 0, i1 = 0

out = 0 (pull0)

pull0 strength (= 5) > weak0 strength (=3)

i0 = 0, i1 = 1

out = x

The out net is driven as 0 (supply0) and 1 (supply1) simultaneously.

i0 = 1, i1 = 0

out = x

The out net is driven as 0 (supply0) and 1 (supply1) simultaneously.

i0 = 1, i1 = 1

out = 1 (supply1)

supply1 strength (= 7) > strong1 strength (=6)

 
module strength(
  input i1, i2,
  output out);
  
  //assign (supply1, pull0) out = (i1 | i2);
  //assign (strong1, supply0) out = i1 & i2;
  
  or (supply1, pull0) o1(out, i1, i2);
  and (strong1, supply0) a1(out, i1, i2);

endmodule

Output:

At time = 0: i1 = 0, i2 = 0 -> out = 0
At time = 1: i1 = 0, i2 = 1 -> out = x
At time = 2: i1 = 1, i2 = 0 -> out = x
At time = 3: i1 = 1, i2 = 1 -> out = 1

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