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Finite State Machine

For combinational designs, the output value completely depends on the present value of the inputs and for sequential designs, output value not only depends on present input but also depends on its previously stored value i.e. past behavior of the design. These sequential designs are formally knowns as finite-state machines that have a fixed number of states. In sequential designs or FSM, a clock signal serves the purpose to control FSM operation. There are two ways to design FSMs.

  1. Mealy Machine
  2. Moore Machine

Difference between Mealy and Moore Machines

Mealy Machine

Moore Machine

Output depends on the present state and current input

Output only depends on the present state. It is independent of current input

Requires fewer states to design

Requires more states to design

Reacts faster to the input and requires less hardware implementation

More logic is required to decode the output.

Difficult to design

Easy to design

Asynchronous output generation even though the states changes in synchronous to the clock.

Synchronous output and state generation w.r.t. clock

Sequence Detector

Both Mealy and Moore machines can be used to design sequence detector logic. Further, these machines are classified as

  1. Overlapping sequence detector – Final bits of the sequence can be the start of another sequence. Thus, it allows overlap.
  2. Non-overlapping sequence detector – Once sequence detection is completed, another sequence detection can be started without any overlap.

Sequence Detector Examples

Verilog Tutorials