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# Procedural continuous assignments

Till now we have seen two types of assignments i.e. continuous assignment and procedural assignment.

The continuous assignment is used to drive net data type variables using the ‘assign’ statements whereas procedural assignments are used to drive reg data type variables using initial and always block statements.

Verilog also provides a third type of assignment i.e. procedural continuous assignment that drives net or reg data type variables for a certain period of time by overriding the existing assignments.

There are two types of procedural continuous assignments

- assign and deassign
- force and release

## assign and deassign

The assign and deassign statements control reg type variable values by overriding existing procedural assignments for a limited time period. After the execution of the deassign statement, another procedural or procedural continuous assignment can change the variable value once again, till then the previous value can hold.

```
module assign_deassign_ex;
reg [3:0] d1;
initial begin
$monitor("At time T = %0t: d1 = %0d", $time, d1);
d1 = 5;
#20 d1 = 7;
end
initial begin
#5;
assign d1 = 3;
#5 deassign d1;
$display("At time T = %0t: deassign d1", $time);
end
endmodule
```

**Output:**

```
At time T = 0: d1 = 5
At time T = 5: d1 = 3
At time T = 10: deassign d1
At time T = 20: d1 = 7
```

The d1 = 3 is assigned at #5 time units and deassign at #10 time units.The d1 = 3 retains till next assignment d1 = 7 happens at 20 time units.

## force and release

The force and release statements control net and reg data type variable values by overriding existing procedural, continuous or procedural continuous assignments for a limited time period. After the execution of the release statement for the reg data type variable, another procedural or procedural continuous assignment can change the variable value once again, till then the previous value can hold. The value of the previous continuous assignment retains in the case of the net data type variable.

```
module assign_deassign_ex;
reg [3:0] d1;
wire [3:0] d2;
assign d2 = 2;
initial begin
$monitor("At time T = %0t: d1 = %0d, d2 = %0d", $time, d1, d2);
d1 = 5;
#20 d1 = 7;
end
initial begin
#5;
$display("At time T = %0t: force d1 and d2", $time);
force d1 = 3;
force d2 = 4;
#5 release d1;
release d2;
$display("At time T = %0t: release d1 and d2", $time);
end
endmodule
```

**Output:**

```
At time T = 0: d1 = 5, d2 = 2
At time T = 5: force d1 and d2
At time T = 5: d1 = 3, d2 = 4
At time T = 10: release d1 and d2
At time T = 10: d1 = 3, d2 = 2
At time T = 20: d1 = 7, d2 = 2
```

The d1 belongs to the reg data type and d2 belongs to the net data type. Both variables are forced at #5 time units and released at #10 time units Once, it is released,

- The d1 value remains the same (d1 = 3) until it is changed to d1 = 7 at 20 time units.
- The d2 value holds a previously assigned value using continuous assignment (d2 = 2).

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