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# Data flow Modeling

Though gate-level modeling is easy to implement for the designs when the number of gates becomes more in the design, it becomes difficult for the implementation. Hence, higher-level abstraction is required for design implementation.

The data flow modeling provides a way to design circuits depending on how data flow between the registers and how data is processed.

## Continuous assignment

In data flow modeling, a continuous assignment is used to drive a value to a net or wire. A continuous assignment statement is represented by an ‘assign’ statement.

**Syntax:**

`assign <drive_strength> <expression or net> = <delay> <constant value or expression>`

Where,

**drive_strength:** driven strength on a wire. It is used to resolve conflict when two or more assignments drive the same net or wire. Refer strength in verilog

**delay:** to specify a delay in an assignment in terms of time units (similar to the delay in gate modeling). It is useful to mimic real-time circuit behavior.

**Note: **

- The drive_strength and delay both are optional to use. The R.H.S. expression is evaluated and assigned to the L.H.S. expression.
- Since ‘assign’ statements are always active, they are known as continuous assignments.
- In an implicit continuous assignment, Verilog provides flexibility to combine net declaration and assign statement. Both regular and implicit continuous assignments have no difference in terms of outcome.

```
//Regular continuous assignment
wire result;
assign result = i1 ^ i2;
//Implicit continuous assignment
wire result = i1 ^ i2;
```

## Rules and characteristics of continuous assignment

- The L.H.S. of an assignment must be always a vector or scalar net or a concatenation of vector or scalar nets. It can not be a vector or scalar register.
- The R.H.S. of an assignment can be registers or nets or function calls. Here, registers or nets can be vectors or scalars.
- Since continuous assignments are always active, as soon as the R.H.S. operand has any changes, it assigns to the L.H.S. operand.

`assign LHS = RHS`

LHS must be

- Vector or scalar net
- Concatenation of vector or scalar net

RHS can be

- Vector or scalar register or net
- Function call

## Delays in continuous assignment

The delay value specified in the ‘assign’ statement controls the timing effect on the L.H.S. operand when the R.H.S. operand has any changes.

Verilog allows specifying delays in three ways and all of them have the same effect.

### A. Regular assignment delay

```
wire result;
assign #5 result = i1 ^ i2;
```

### B. Implicit continuous assignment delay

`wire #5 result = i1 ^ i2;`

### C. Net declaration delay

```
wire #5 result;
assign result = i1 ^ i2;
```

## Data flow Modeling Example

```
module dataflow_modeling(
input i1, i2,
output [4:0] result
);
assign result[0] = i1^i2;
assign #5 result[1] = i1^i2;
assign result[3:2] = {i1, i2};
endmodule
```

**Output:**

```
0: i1 = x, i2 = x, result = zxxxx
1: i1 = 0, i2 = 0, result = z00x0
6: i1 = 0, i2 = 1, result = z0101
11: i1 = 1, i2 = 0, result = z1011
16: i1 = 1, i2 = 1, result = z1110
21: i1 = 1, i2 = 1, result = z1100
```

**Explanation:**

The result is a 5-bit output variable and only [3:0] bits are updated with the ‘assign’ statement. Hence, the 4th-bit position will remain ‘Z’ always.

At 0 time units, no inputs are driven i.e. i1 = x and i2 = x that results in result = zxxxx.

At 1 time units, i1 = 0 and i2 = 0, result[1] will be updated after 5 time units, hence the value of result[1] = x. Other bit positions 0th, 2nd, 3rd and 4th of the result vector has updated values.

Similarly, for remaining input combinations [3:0] bits have updated values.

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