Tutorials

Verilog operators

The Verilog operators are similar to the C programming language operator that is used to produce results based on the required operation.

Verilog provides different categories of operators

1. Arithmetic operators

 Operators Number of operands Description + 2 addition – 2 subtraction * 2 multiplication / 2 division ** 2 raised to the power % 2 modulus produces the remainder of the division of two numbers. The outcome takes the sign of the first operand.

The arithmetic operator performs an arithmetic operation on two operands.

Example:

``````module arithmetic_op;
reg [3:0] i1, i2;
initial begin
i1 = 4'h6;
i2 = 4'h2;

\$display("i1 = %0h and i2 = %0h", i1, i2);
\$display("Sub: %0h", i1 - i2);
\$display("Mul: %0h", i1 * i2);
\$display("Div: %0h", i1 / i2);
\$display("pow: %0h", i2 ** 3);
\$display("Mod: %0h", i1 % i2);

i1 = 4'ha; i2 = 4'h3;
\$display("\ni1 = %0h and i2 = %0h", i1, i2);
\$display("Mod: %0h", i1 % i2);
end
endmodule``````

Output:

``````i1 = 6 and i2 = 2
Sub: 4
Mul: c
Div: 3
pow: 8
Mod: 0

i1 = a and i2 = 3
Mod: 1``````

2. Logical operators

 Operators Number of operands Description ! 1 logical negation && 2 logical and || 2 logical or

Logical operators take variables or expressions as operands and it evaluates to 0, 1, or x value.

Example:

``````module logical_op;
reg [3:0] i1, i2;
initial begin
i1 = 4'h6; i2 = 4'h2;
\$display("For operator: (&&): i1 = %0h && i2 = %0h: %h", i1, i2, i1 && i2);
\$display("For operator: (||): i1 = %0h || i2 = %0h: %h", i1, i2, i1 || i2);
\$display("For operator: (!) : i1 = %0h !  i2 = %0h: %h", i1, i2, !i1);

i1 = 4'b1x0z; i2 = 4'b0x1x;
\$display("For operator: (&&): i1 = %0b && i2 = %0b: %h", i1, i2, i1 && i2);
\$display("For operator: (||): i1 = %0b || i2 = %0b: %h", i1, i2, i1 || i2);
end
endmodule``````

Output:

``````For operator: (&&): i1 = 6 && i2 = 2: 1
For operator: (||): i1 = 6 || i2 = 2: 1
For operator: (!) : i1 = 6 !  i2 = 2: 0
For operator: (&&): i1 = 1x0z && i2 = x1x: 1
For operator: (||): i1 = 1x0z || i2 = x1x: 1``````

3. Equality operators

 Operators Number of operands Description == 2 equality != 2 inequality === 2 case equality !== 2 case inequality

The equality and inequality operator compares two operands bit by bit and results to 1 or 0 if true or false respectively. They will return value as ‘x’ if either operand has x or z bits.

The case equality and case inequality compares two operands bit by bit even for x and z bits and results in 1 or 0 if true or false respectively. They perform an exact bit-by-bit comparison. If any of the bits is not matched, the result will be 0 (false).

Note:

1. For unequal length in operands, it fills zeroes at MSB, and a comparison is performed.
2. The key difference between equality and case equality is in terms of producing results. The case equality never produces an ‘x’ result whereas equality will produce an ‘x’ result if any of the operands has ‘x’ bits.

Example:

``````module equality_op;
reg [3:0] i1, i2;
initial begin
i1 = 4'h6; i2 = 4'h2;
\$display("For operator: (==): (i1 = %0h) == (i2 = %0h) --> %h", i1, i2, i1 == i2);
\$display("For operator: (!=): (i1 = %0h) != (i2 = %0h) --> %h", i1, i2, i1 != i2);

i1 = 4'b1x0z; i2 = 4'b1x0z;
\$display("For operator: (==) : (i1 = %0b) ==  (i2 = %0b) --> %0b", i1, i2, i1 == i2);
\$display("For operator: (!=) : (i1 = %0b) !=  (i2 = %0b) --> %0b", i1, i2, i1 != i2);

\$display("For operator: (===) : (i1 = %0b) ===  (i2 = %0b) --> %0b", i1, i2, i1 === i2);
\$display("For operator: (!==) : (i1 = %0b) !==  (i2 = %0b) --> %0b", i1, i2, i1 !== i2);

i1 = 4'b1x0z; i2 = 4'b1x0x;
\$display("For operator: (===) : (i1 = %0b) ===  (i2 = %0b) --> %0b", i1, i2, i1 === i2);
\$display("For operator: (!==) : (i1 = %0b) !==  (i2 = %0b) --> %0b", i1, i2, i1 !== i2);
end
endmodule``````

Output:

``````For operator: (==): (i1 = 6) == (i2 = 2) --> 0
For operator: (!=): (i1 = 6) != (i2 = 2) --> 1
For operator: (==) : (i1 = 1x0z) ==  (i2 = 1x0z) --> x
For operator: (!=) : (i1 = 1x0z) !=  (i2 = 1x0z) --> x
For operator: (===) : (i1 = 1x0z) ===  (i2 = 1x0z) --> 1
For operator: (!==) : (i1 = 1x0z) !==  (i2 = 1x0z) --> 0
For operator: (===) : (i1 = 1x0z) ===  (i2 = 1x0x) --> 0
For operator: (!==) : (i1 = 1x0z) !==  (i2 = 1x0x) --> 1``````

4. Relational operators

 Operators Number of operands Description > 2 greater than >= 2 greater than or equal to < 2 less than <= 2 less than or equal to

The relational operation is performed on two operands to returns 1 if the expression is true, otherwise returns 0 if the expression is false.

Note: The ‘z’ is treated as ‘x’ in a relational operation.

Example:

``````module relational_op;
reg [3:0] i1, i2;
initial begin
i1 = 4'h6; i2 = 4'h2;
\$display("For operator: (>) : i1 = %0h >  i2 = %0h: %h", i1, i2, i1>i2);
\$display("For operator: (>=): i1 = %0h >= i2 = %0h: %h", i1, i2, i1>=i2);
\$display("For operator: (<) : i1 = %0h <  i2 = %0h: %h", i1, i2, i1<i2);

i1 = 4'h2; i2 = 4'h6;
\$display("For operator: (<) : i1 = %0h <  i2 = %0h: %h", i1, i2, i1<i2);
\$display("For operator: (<=): i1 = %0h <= i2 = %0h: %h", i1, i2, i1<=i2);
\$display("For operator: (>) : i1 = %0h >  i2 = %0h: %h", i1, i2, i1>i2);
end
endmodule``````

Output:

``````For operator: (>) : i1 = 6 >  i2 = 2: 1
For operator: (>=): i1 = 6 >= i2 = 2: 1
For operator: (<) : i1 = 6 <  i2 = 2: 0
For operator: (<) : i1 = 2 <  i2 = 6: 1
For operator: (<=): i1 = 2 <= i2 = 6: 1
For operator: (>) : i1 = 2 >  i2 = 6: 0``````

5. Bitwise operators

 Operators Number of operands Description & 2 bitwise and | 2 bitwise or ^ 2 bitwise xor ~ 1 bitwise negation ^~ or ~^ 2 bitwise xnor

The bitwise operator performs bit by bit operation on one operand and a corresponding bit on the other operand. For any mismatch in length, extra zeros are appended.

Note:

1. The ‘z’ is treated as ‘x’ in a bitwise operation.
2. The bitwise operators (&, |, ~) performs bit-by-bit operation whereas logical operator (&&, ||, ! ) performs a logical operation.

The bitwise operator follows the below truth table in an operation.

Bitwise and operator

 & 0 1 x or z 0 0 0 0 1 0 1 x x or z 0 x x

Bitwise or operator

 | 0 1 x or z 0 0 1 x 1 1 1 1 x or z x 1 x

Bitwise xor operator

 ^ 0 1 x or z 0 0 1 x 1 1 0 x x or z x x x

Bitwise xnor operator

 ~^ 0 1 x or z 0 0 1 x 1 1 1 1 x or z x 1 x

negation Operator

 ~ result 0 1 1 0 x or z x
``````module bitwise_op;
reg [3:0] i1, i2;
initial begin
i1 = 4'h6; i2 = 4'h2;
\$display("For operator: (&) : i1 = %b &  i2 = %b: %h", i1, i2, i1 & i2);
\$display("For operator: (|) : i1 = %b |  i2 = %b: %h", i1, i2, i1 | i2);
\$display("For operator: (^) : i1 = %b ^  i2 = %b: %h", i1, i2, i1 ^ i2);
\$display("For operator: (~) : i1 = %b ~  i2 = %b: %h", i1, i2, ~i1);
\$display("For operator: (~^): i1 = %b ~^ i2 = %b: %h", i1, i2, i1 ~^ i2);

i1 = 4'b1x0z; i2 = 4'b0x1x;
\$display("For operator: (&) : i1 = %b &  i2 = %b: %b", i1, i2, i1 & i2);
\$display("For operator: (|) : i1 = %b |  i2 = %b: %b", i1, i2, i1 | i2);
\$display("For operator: (^) : i1 = %b ^  i2 = %b: %b", i1, i2, i1 ^ i2);
\$display("For operator: (~) : i1 = %b ~  i2 = %b: %b", i1, i2, ~i1);
\$display("For operator: (~^): i1 = %b ~^ i2 = %b: %b", i1, i2, i1 ~^ i2);
end
endmodule``````

Output:

``````For operator: (&) : i1 = 0110 &  i2 = 0010: 2
For operator: (|) : i1 = 0110 |  i2 = 0010: 6
For operator: (^) : i1 = 0110 ^  i2 = 0010: 4
For operator: (~) : i1 = 0110 ~  i2 = 0010: 9
For operator: (~^): i1 = 0110 ~^ i2 = 0010: b
For operator: (&) : i1 = 1x0z &  i2 = 0x1x: 0x0x
For operator: (|) : i1 = 1x0z |  i2 = 0x1x: 1x1x
For operator: (^) : i1 = 1x0z ^  i2 = 0x1x: 1x1x
For operator: (~) : i1 = 1x0z ~  i2 = 0x1x: 0x1x
For operator: (~^): i1 = 1x0z ~^ i2 = 0x1x: 0x0x``````

6. Conditional operators

 Operators Number of operands Description ?: 3 conditional

Syntax:

``<result> = <conditional_expression> ? <true_expression> : <false_expression>``

Evaluation:

The <conditional_expression> is evaluated first. If the result is

1. True, then <true_expression> is evaluated.
2. False, then <false_expression> is evaluated.
3. X (ambiguous ) then both <true_expression> and <false_expression> are evaluated and their results are compared bit by bit. Each bit position of outcome is returned as
a.
bit value if both bits are the same.
b. X if bit value differs.

Examples:

``````module conditional_op;
reg [3:0] i1, i2;
reg [3:0] result;
initial begin
i1 = 4'h6; i2 = 4'h2;
\$display("i1 = %0h, i2 = %0h", i1, i2);
result = (i1 > i2)? 1 : 0;
\$display("result = %0h", result);

i1 = 4'h6; i2 = 4'h6;
\$display("i1 = %0h, i2 = %0h", i1, i2);
result = (i1 > i2)? 1 : 0;
\$display("result = %0h", result);

i1 = 4'b1x00; i2 = 4'b0100;
\$display("i1 = %b, i2 = %b", i1, i2);
result = (i1 > i2)? (i1 & i2) : (i1 | i2);
// The outcome is ambiguous then both <true_expression> and <false_expression>
// will be evaluated and compared to compute outcome
// <true_expression>  = i1 & i2 = 4'b0x00
// <false_expression> = i1 | i2 = 4'b1x00
// result = xx00;
\$display("result = %b", result);
end
endmodule``````

Output:

``````i1 = 6, i2 = 2
result = 1
i1 = 6, i2 = 6
result = 0
i1 = 1x00, i2 = 0100
result = xx00``````

2:1 MUX or tri-state buffer can be easily implemented by a conditional operator.

2:1 MUX implementation

``````module mux_2_1(
input sel,
input i0, i1,
output y);

assign y = sel ? i1 : i0;
endmodule``````

Output:

``````sel = 0: i0 = 0, i1 = 1 --> y = 0
sel = 1: i0 = 0, i1 = 1 --> y = 1``````

Tri-state buffer implementation

``````module tristate_buff(
input in,
input en,
output out);

assign out = en ? in : 1'bz;
endmodule``````

Output:

``````en = 0: in = 0 --> out = z
en = 1: in = 0 --> out = 0
en = 1: in = 1 --> out = 1``````

7. Shift operators

 Operators Number of operands Description << 2 logical left shift >> 2 logical right shift <<< 2 arithmetic left shift >>> 2 arithmetic right shift

Logical shift: Logical shift operators shift a vector to left or right by a specified number of bits and fill vacant bit positions with zeros.

Arithmetic shift: Arithmetic shift operators shift a vector to left or right by a specified number of bits and fill vacant bit positions with sign bit if an expression is signed, otherwise with zeros.

Note: Shift operators do not wrap around.

``````module shift_op;
reg [7:0] i1, o1;
reg signed [7:0] i2, o2;

initial begin
// Logical shift
i1 = 8'b1111_0000;
o1 = i1 >> 3;
\$display("Shift right (>>) i1 = %b by 3: %b", i1, o1);
i1 = o1;

o1 = i1 << 3;
\$display("Shift left (<<) i1 = %b by 3: %b", i1, o1);

// Arithmatic shift
i2 = 8'b1111_0000;
o2 = i2 >>> 3;
\$display("Shift right (>>>) i2 = %b by 3: %b", i2, o2);
i2 = o2;

o2 = i2 <<< 3;
\$display("Shift left (<<<) i2 = %b by 3: %b", i2, o2);
end
endmodule``````

Output:

``````Shift right (>>) i1 = 11110000 by 3: 00011110
Shift left (<<) i1 = 00011110 by 3: 11110000
Shift right (>>>) i2 = 11110000 by 3: 11111110
Shift left (<<<) i2 = 11111110 by 3: 11110000``````

8. Reduction operators

 Operators Number of operands Description & 1 reduction and | 1 reduction or ^ 1 reduction xor ~& 1 reduction nand ~| 1 reduction nor ^~ or ~^ 1 reduction xnor

The reduction operators give 1-bit output by performing the bitwise operation over a single vector operand.

Note:

1. Reduction operators work bit by bit from right to left.
2. Results of reduction nand, reduction nor and reduction xnor are inverted versions of results of reduction and, reduction or and reduction xor.
``````module reduction_op;
reg [3:0] i1;
initial begin
i1 = 4'h6;
\$display("For operator: (&)  : i1 = %b -> %b", i1, &i1);
\$display("For operator: (|)  : i1 = %b -> %b", i1, |i1);
\$display("For operator: (^)  : i1 = %b -> %b", i1, ^i1);
\$display("For operator: (~&) : i1 = %b -> %b", i1, ~&i1);
\$display("For operator: (~|) : i1 = %b -> %b", i1, ~|i1);
\$display("For operator: (~^) : i1 = %b -> %b", i1, ~^i1);

i1 = 4'b1x0z;
\$display("For operator: (&)  : i1 = %b -> %b", i1, &i1);
\$display("For operator: (|)  : i1 = %b -> %b", i1, |i1);
\$display("For operator: (^)  : i1 = %b -> %b", i1, ^i1);
\$display("For operator: (~&) : i1 = %b -> %b", i1, ~&i1);
\$display("For operator: (~|) : i1 = %b -> %b", i1, ~|i1);
\$display("For operator: (~^) : i1 = %b -> %b", i1, ~^i1);
end
endmodule``````

Output:

``````For operator: (&)  : i1 = 0110 -> 0
For operator: (|)  : i1 = 0110 -> 1
For operator: (^)  : i1 = 0110 -> 0
For operator: (~&) : i1 = 0110 -> 1
For operator: (~|) : i1 = 0110 -> 0
For operator: (~^) : i1 = 0110 -> 1
For operator: (&)  : i1 = 1x0z -> 0
For operator: (|)  : i1 = 1x0z -> 1
For operator: (^)  : i1 = 1x0z -> x
For operator: (~&) : i1 = 1x0z -> 1
For operator: (~|) : i1 = 1x0z -> 0
For operator: (~^) : i1 = 1x0z -> x``````

9. Concatenation operators

 Operators Number of operands Description {  } ‘N’ number concatenation

The multiple operands can be appended using a concatenation operator. The operands have to be written in braces and separate themselves with commas.

Note:

1. Operands can be vector/scalar registers or nets, sized constants, bit-select.
2. Unsized operands are not allowed because computed result size is dependent on each operand size.
``````module concatenation_op;
reg [1:0] i1, i2;
reg [3:0] i3;
reg [7:0] out;

initial begin
i1 = 2'h2; i2 = 2'h3;
i3 = 4'h8;

\$display("out = %b", {i3, i2, i1});
\$display("out = %b", {i3, i2, 2'b11});
\$display("out = %b", {i3, i2[1], 1'b1, i1[0]});
end
endmodule``````

Output:

``````out = 10001110
out = 10001111
out = 1000110``````

10. Replication operators

 Operators Number of operands Description {  {  }  } ‘N’ number replication

The same number can be replicated for a specific number of times (replication constant) using a replication operator.

``````module replication_op;
reg [1:0] i1, i2;
reg [7:0] out;

initial begin
i1 = 2'h2; i2 = 2'h3;

\$display("out = %b", {4{i1}});
\$display("out = %b", {{3{i2}}, {2{i1}}} );
end
endmodule``````

Output:

``````out = 10101010
out = 1111111010``````

Note:

1. It is recommended to use parentheses in the expressions to avoid ambiguity.
2. If parentheses are not used then precedence order is followed as

Arithmetic operator (Highest precedence) -> Relational operator -> equality operator -> reduction operator -> logical operator -> conditional operator (Lowest precedence).

Verilog Tutorials