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The assertion can be written as a part of the design code. A designer or verification engineer can plan for adding an assertion. It is not a flexible and recommended way to have assertions in the design files since designers do want to change their code by the verification team. SystemVerilog provides flexibility to write assertions in separate files in the testbench and then bind the same design file.

The ‘bind’ directive allows binding assertions with

  1. Design module
  2. Interface 

Binding is possible with

  1. A specific instance of a module or interface
  2. All instances of a module or interface

Syntax:

To bind with specific instance

bind <dut_specific_instance_path> <assertion_module> <instance>

To bind with all instances

bind <dut_module> <assertion_module> <instance>

bind example

assertion.sv

module assertion_dff (
  input clk, rst_n, d, q
);
  
  sequence seq1;
    d ##1 q;
  endsequence 
  
  property prop;
    @(posedge clk) disable iff(rst_n)
    d |=> seq1;
  endproperty
  
  dff_assert: assert property (prop) else $display("Assertion failed at time = %0t", $time);
endmodule
`include "assertion.sv"
module tb;
  reg clk, rst_n;
  reg d;
  wire q;
  
  D_flipflop dff1(clk, rst_n, d, q);
  D_flipflop dff2(clk, rst_n, d, q);
  
  // To bind with all instances of DUT
  bind D_flipflop assertion_dff all_inst(clk, rst_n, d, q);
  
  // To bind with single instance of DUT
  bind tb.dff2 assertion_dff single_inst(clk, rst_n, d, q);
  
  always #2 clk = ~clk;
  initial begin
    clk = 0; rst_n = 0;
    d = 0;
    
    #3 rst_n = 1;
    
    repeat(6) begin
      d = $urandom_range(0, 1);
      #3 rst_n = $urandom_range(0, 1);
    end
    $finish;
  end
  
  initial begin
    $monitor("At time = %0t: rst_n = %b, d = %b, q = %b", $time, rst_n, d, q);
  end
endmodule

Output:

At time = 0: rst_n = 0, d = 0, q = x
At time = 2: rst_n = 0, d = 0, q = 0
At time = 3: rst_n = 1, d = 1, q = 0
At time = 6: rst_n = 0, d = 1, q = 0
At time = 9: rst_n = 1, d = 0, q = 0
At time = 15: rst_n = 0, d = 0, q = 0
At time = 18: rst_n = 1, d = 1, q = 1

SystemVerilog Assertions