Tutorials

Learn More

The clock can be specified for properties in several ways.

Rules: The clock for an assertion is determined based on the priority mentioned below.

Priority 1: Use the explicitly mentioned clock for the assertion.

Priority 2: Infer clock from code context where it is used.

Priority 3: Use default specified clock.

Note: It is mandatory to mention the clock in case of concurrent assertion. If a clock is not used, statements are considered to be illegal.

Ways to specify the clock

Property has a clock defined

sequence seqA
  req1 ##3 req2;
endsequence

property prop;
  @(posedge clk) seqA;
endproperty

assert property (prop);

Sequence has a clock defined

sequence seqA
  @(posedge clk) req1 ##3 req2;
endsequence

property prop;
  seqA;
endproperty

assert property (prop);

Infer clock from clocking block

clocking CB @(posedge clk);
  property prop;
    req1 ##3 req2;
  endproperty
endclocking

assert property (CB.prop);

Infer clock from procedural block 

property prop;
  req1 ##3 req2;
endproperty

always @(posedge clk) assert property (prop);

SystemVerilog Assertions