Expect statement in an assertion
The expect statement is a procedural blocking statement that is similar to an assert statement and used to block the execution until the property is evaluated. It must be used with procedural blocks like always, initial blocks, tasks, and functions.
Difference between assert and expect statement
An expect statement works in a procedural way like a single thread that unblocks after property evaluation (does not matter success or fail) whereas assert works concurrently like a separate thread and behaves in a non-blocking manner.
Syntax:
expect (property or sequence) <statements>
Usage: To execute some procedural code after a series of sequences.
Note: The “expect” statement does not infer the clock from its procedural block, it has to be explicitly specified in the sequence/ property or within the expect statement.
Example 1: clock specified within the expect statement
initial begin
#100;
expect(@(posedge clk) req1 ##2 req2) else $error "expect failure");
<statement>;
end
Example 2: clock specified within the property block
property prop;
@(posedge clk) req1 ##2 req2;
endproperty
initial begin
#100;
expect prop else $error "expect failure");
<statement>;
end
After 100 time units, whenever posedge of a clock happens, req1 is true, followed by 2 clock cycles, req2 is true to pass the expect statement (otherwise, it fails), and then only <statement> can be executed.
SystemVerilog Assertions