first_match Operator
The first_match operator matches only for the first match out of all possible multiple matches.
Syntax:
first_match(<seq_exp>)
The evaluation attempt for seq_expression happens on the same clock cycle when the first_match operator is evaluated.
The first_match(<seq_exp>) produces no match when <seq_exp> produces no match The first_match(<seq_exp>) produces a match when the earliest match happens for <seq_exp> for the same clock tick.
first_match operator example
sequence seq;
first_match(req1 ## [1:4] req2);
endsequence
This is equivalent to
req1 ##1 req2
req1 ##2 req2
req1 ##3 req2
req1 ##4 req2
Out of the above 4 expressions, whichever matches first is said to be matched for the sequence seq.
module assertion_example;
bit clk, req1, req2;
always #2 clk = ~clk;
sequence seq;
first_match(req1 ##[1:4] req2);
//req1 ##[1:4] req2;
endsequence
property prop;
@(posedge clk) seq;
endproperty
label_a: assert property(prop) $info("passed at %0t",$time);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
req1 = 0;
req2 = 0;
#2 req1 = 1;
#4 req2 = 1;
#4 req1 = 0;
#4 req2 = 0;
#15 req1 = 0;
#15 req2 = 0;
#20; $finish;
end
endmodule
Output:
"testbench.sv", 17: assertion_example.label_a: started at 2ns failed at 2ns
Offending 'req1'
Info: "testbench.sv", 17: assertion_example.label_a: at time 10 ns
passed at 10
"testbench.sv", 17: assertion_example.label_a: started at 14ns failed at 14ns
Offending 'req1'
Info: "testbench.sv", 17: assertion_example.label_a: at time 14 ns
passed at 14
"testbench.sv", 17: assertion_example.label_a: started at 18ns failed at 18ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 22ns failed at 22ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 26ns failed at 26ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 30ns failed at 30ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 34ns failed at 34ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 38ns failed at 38ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 42ns failed at 42ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 46ns failed at 46ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 50ns failed at 50ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 54ns failed at 54ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 58ns failed at 58ns
Offending 'req1'
"testbench.sv", 17: assertion_example.label_a: started at 62ns failed at 62ns
Offending 'req1'
$finish called from file "testbench.sv", line 33.
SystemVerilog Assertions