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if expression in property
The if(expression) is used to select property expressions based on the if condition.
It is generally used in properties with implication operator-based assertions.
Syntax:
if(expression)
<property_exp1>
else
<property_exp2>;
if expression in property example
property prop;
@(posedge clk) (req1 || req2) |->
if(req1)
(##1 ack1)
else
(##2 ack2);
endproperty
ended in sequence
The endpoint of sequence detection returns true if the previously started sequence (another sequence) reaches the endpoint when the current sequence is under execution at that particular point in time else it returns false.
Syntax:
<sequence>.ended
ended in sequence example
sequence seq1;
@(posedge clk) $rose(en) ##1 req1 ## req2;
endsequence
sequence seq2;
@(posedge clk) reset ##2 seq1.ended ##1 ack;
endsequence
Once reset goes high, after 2 clock cycles seq1 has to be ended and after 1 clock cycle ack is expected to come.
SystemVerilog Assertions