Put Interface Examples

The producer controls the flow of transactions. All methods put, try_put, and can_put have to be implemented in the consumer, and method calls need to be called from the producer.

Imp port has an implementation of the method.

uvm_put_port/ imp using int

`include "uvm_macros.svh"
import uvm_pkg::*;

class producer extends uvm_component;
  uvm_put_port#(int) tlm_put;
  
  `uvm_component_utils(producer)
  
  function new(string name = "producer", uvm_component parent = null);
    super.new(name, parent);
    tlm_put = new("tlm_put", this);
  endfunction
  
  task run_phase(uvm_phase phase);
    int value = 10;
    super.run_phase(phase);
    
    `uvm_info(get_type_name(), $sformatf("Send value = %0h", value), UVM_NONE);
    tlm_put.put(value);
    tlm_put.try_put(20);
    tlm_put.can_put();
  endtask
endclass

class consumer extends uvm_component;
  uvm_put_imp #(int, consumer) tlm_imp;
   
  `uvm_component_utils(consumer)
  
  function new(string name = "consumer", uvm_component parent = null);
    super.new(name, parent);
    tlm_imp = new("tlm_imp", this);
  endfunction
  
  virtual task put(int val);
    #10;
    `uvm_info(get_type_name(), $sformatf("Received value = %0h", val), UVM_NONE);
  endtask
  
  virtual function bit try_put(int val);
    `uvm_info(get_type_name(), $sformatf("Received try_put value = %0h", val), UVM_NONE);
    return 1;
  endfunction
  
  virtual function bit can_put();
    `uvm_info(get_type_name(), "inside can_put", UVM_NONE);
    return 1;
  endfunction
endclass

class env extends uvm_env;
  producer pro;
  consumer con;
  `uvm_component_utils(env)
  
  function new(string name = "env", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    pro = producer::type_id::create("pro", this);
    con = consumer::type_id::create("con", this);
  endfunction
  
  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    pro.tlm_put.connect(con.tlm_imp);
  endfunction
endclass
              
class test extends uvm_test;
  env env_o;
  `uvm_component_utils(test)
  
  function new(string name = "test", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env_o = env::type_id::create("env_o", this);
  endfunction
 
  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    #50;
    phase.drop_objection(this);
  endtask
endclass

module tb_top;
  initial begin
    run_test("test");
  end
endmodule

Output:

UVM_INFO testbench.sv(18) @ 0: uvm_test_top.env_o.pro [producer] Send value = a
UVM_INFO testbench.sv(37) @ 10: uvm_test_top.env_o.con [consumer] Received value = a
UVM_INFO testbench.sv(41) @ 10: uvm_test_top.env_o.con [consumer] Received try_put value = 14
UVM_INFO testbench.sv(46) @ 10: uvm_test_top.env_o.con [consumer] inside can_put

uvm_put_port/ imp using transaction item

`include "uvm_macros.svh"
import uvm_pkg::*;

class seq_item extends uvm_sequence_item;
  rand bit [3:0] value;
  `uvm_object_utils(seq_item)
  
  function new(string name = "seq_item");
    super.new(name);
  endfunction
endclass

class producer extends uvm_component;
  uvm_put_port#(seq_item) tlm_put;
  seq_item req;
  `uvm_component_utils(producer)
  
  function new(string name = "producer", uvm_component parent = null);
    super.new(name, parent);
    tlm_put = new("tlm_put", this);
  endfunction
  
  task run_phase(uvm_phase phase);
    super.run_phase(phase);
    
    req = seq_item::type_id::create("req");
    assert(req.randomize());
    `uvm_info(get_type_name(), $sformatf("Send value = %0h", req.value), UVM_NONE);
    
    tlm_put.put(req);
    
    assert(req.randomize());
    `uvm_info(get_type_name(), $sformatf("For try_put: Send value = %0h", req.value), UVM_NONE);
    tlm_put.try_put(req);
    tlm_put.can_put();
  endtask
endclass

class consumer extends uvm_component;
  uvm_put_imp #(seq_item, consumer) tlm_imp;
   
  `uvm_component_utils(consumer)
  
  function new(string name = "consumer", uvm_component parent = null);
    super.new(name, parent);
    tlm_imp = new("tlm_imp", this);
  endfunction
  
  virtual task put(seq_item trans);
    #10;
    `uvm_info(get_type_name(), $sformatf("Received value = %0h", trans.value), UVM_NONE);
  endtask
  
  virtual function bit try_put(seq_item trans);
    `uvm_info(get_type_name(), $sformatf("Received try_put value = %0h", trans.value), UVM_NONE);
    return 1;
  endfunction
  
  virtual function bit can_put();
    `uvm_info(get_type_name(), "inside can_put", UVM_NONE);
    return 1;
  endfunction
endclass

class env extends uvm_env;
  producer pro;
  consumer con;
  `uvm_component_utils(env)
  
  function new(string name = "env", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    pro = producer::type_id::create("pro", this);
    con = consumer::type_id::create("con", this);
  endfunction
  
  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    pro.tlm_put.connect(con.tlm_imp);
  endfunction
endclass
              
class test extends uvm_test;
  env env_o;
  `uvm_component_utils(test)
  
  function new(string name = "test", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env_o = env::type_id::create("env_o", this);
  endfunction
 
  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    #50;
    phase.drop_objection(this);
  endtask
endclass

module tb_top;
  initial begin
    run_test("test");
  end
endmodule

Output:

UVM_INFO testbench.sv(28) @ 0: uvm_test_top.env_o.pro [producer] Send value = 0
UVM_INFO testbench.sv(51) @ 10: uvm_test_top.env_o.con [consumer] Received value = 0
UVM_INFO testbench.sv(33) @ 10: uvm_test_top.env_o.pro [producer] For try_put: Send value = d
UVM_INFO testbench.sv(55) @ 10: uvm_test_top.env_o.con [consumer] Received try_put value = d
UVM_INFO testbench.sv(60) @ 10: uvm_test_top.env_o.con [consumer] inside can_put

uvm_blocking_put_port/ imp using transaction item

`include "uvm_macros.svh"
import uvm_pkg::*;

`include "seq_item.sv"

class producer extends uvm_component;
  seq_item req;
  uvm_blocking_put_port #(seq_item) tlm_put;
  
  `uvm_component_utils(producer)
  
  function new(string name = "producer", uvm_component parent = null);
    super.new(name, parent);
    tlm_put = new("tlm_put", this);
  endfunction
  
  task run_phase(uvm_phase phase);
    super.run_phase(phase);
    
    req = seq_item::type_id::create("req");
    assert(req.randomize());
    tlm_put.put(req);
    `uvm_info(get_name(), $sformatf("Send value = %0h", req.value), UVM_NONE);
  endtask
endclass

class consumer extends uvm_component;
  seq_item req;
  uvm_blocking_put_imp #(seq_item, consumer) put_imp;
  
  `uvm_component_utils(consumer)
  
  function new(string name = "consumer", uvm_component parent = null);
    super.new(name, parent);
    put_imp = new("put_imp", this);
  endfunction
  
  virtual function bit put(seq_item req);
    `uvm_info(get_type_name(), $sformatf("Received value = %0h", req.value), UVM_NONE);
    return 1;
  endfunction
endclass

class env extends uvm_env;
  producer pro;
  consumer con;
  `uvm_component_utils(env)
  
  function new(string name = "env", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    pro = producer::type_id::create("pro", this);
    con = consumer::type_id::create("con", this);
  endfunction
  
  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    pro.tlm_put.connect(con.put_imp);
  endfunction
endclass
              
class test extends uvm_test;
  env env_o;
  `uvm_component_utils(test)
  
  function new(string name = "test", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env_o = env::type_id::create("env_o", this);
  endfunction
 
  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    #50;
    phase.drop_objection(this);
  endtask
endclass

module tb_top;
  initial begin
    run_test("test");
  end
endmodule

Output:

UVM_INFO testbench.sv(39) @ 0: uvm_test_top.env_o.con [consumer] Received value = 5
UVM_INFO testbench.sv(23) @ 0: uvm_test_top.env_o.pro [pro] Send value = 5

uvm_nonblocking_put_port/ imp using transaction item

`include "uvm_macros.svh"
import uvm_pkg::*;

`include "seq_item.sv"

class producer extends uvm_component;
  seq_item req;
  uvm_nonblocking_put_port #(seq_item) tlm_put;
  
  `uvm_component_utils(producer)
  
  function new(string name = "producer", uvm_component parent = null);
    super.new(name, parent);
    tlm_put = new("tlm_put", this);
  endfunction
  
  task run_phase(uvm_phase phase);
    super.run_phase(phase);
    
    req = seq_item::type_id::create("req");
    assert(req.randomize());
    `uvm_info(get_type_name(), $sformatf("Send value = %0h", req.value), UVM_NONE);
    tlm_put.try_put(req);
  endtask
endclass

class consumer extends uvm_component;
  seq_item req;
  uvm_nonblocking_put_imp #(seq_item, consumer) tlm_imp;
  
  `uvm_component_utils(consumer)
  
  function new(string name = "consumer", uvm_component parent = null);
    super.new(name, parent);
    tlm_imp = new("tlm_imp", this);
  endfunction
  
  virtual function bit try_put(seq_item req);
    `uvm_info(get_type_name(), $sformatf("Received value = %0h", req.value), UVM_NONE);
    return 1;
  endfunction
  
  virtual function bit can_put();
    return 1;
  endfunction
endclass

class env extends uvm_env;
  producer pro;
  consumer con;
  `uvm_component_utils(env)
  
  function new(string name = "env", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    pro = producer::type_id::create("pro", this);
    con = consumer::type_id::create("con", this);
  endfunction
  
  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    pro.tlm_put.connect(con.tlm_imp);
  endfunction
endclass
              
class test extends uvm_test;
  env env_o;
  `uvm_component_utils(test)
  
  function new(string name = "test", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env_o = env::type_id::create("env_o", this);
  endfunction
 
  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    #50;
    phase.drop_objection(this);
  endtask
endclass

module tb_top;
  initial begin
    run_test("test");
  end
endmodule

Output:

UVM_INFO testbench.sv(22) @ 0: uvm_test_top.env_o.pro [producer] Send value = 0
UVM_INFO testbench.sv(39) @ 0: uvm_test_top.env_o.con [consumer] Received value = 0

TLM Tutorials