Tutorials
Learn More
Verilog Interview Questions
The most frequently asked Verilog interview questions are listed below
Basic Level Questions
- Difference between blocking and non-blocking assignments
- Difference between task and function
- Difference between wire and reg
- What is generate block in Verilog and its usage?
- Difference between while and do-while loop
- What is an automatic keyword in the task?
- Difference between combination and sequential circuits.
- Difference between flip-flop and latch.
- Explain the difference between a static and automatic variable with example.
- Difference between Mealy and Moore FSM.
- Implement XOR gate using 2:1 MUX
- Implement OR gate using 2:1 MUX
- Difference between $stop and $finish.
- Design frequency/2 circuit using DFF.
- Difference between $random and $urandom
Intermediate level questions
- What is the default value of wire and reg?
- Explain inertial delay and transport delay.
- Difference between inter and intra assignment delay
- Difference between full and parallel case
- Difference between casex and casez
- Can you implement DFF in synchronous and asynchronous mode?
- What is #0 in Verilog and its usage?
- How to generate two different clocks in testbench?
- Implement flip-flop using 2:1 MUX
- Design overlapping and non-overlapping FSM for sequence detector 1010.
- Design Mod-3 counter and draw its waveform.
- Write a Verilog code for D-Latch.
- How can you override the existing parameter value?
- What is Synthesis?
- Write an RTL code to generate 60% duty cycle clock.
- Write an RTL code to generate 100MHz clock.
- Difference between `define and `include.
- What is force and release in Verilog?
- What will be output of the following code
always@(clock) begin
a = 0;
a <= 1;
$display(a);
end
Difficult level questions
- Why always block is not used inside a program block?
- What is FIFO and write Verilog code for the design?
- What will happen if there is no else part in if-else?
- Explain overflow and underflow in FIFO.
- What are all different applications of FIFO?
- Swap register content with and without using an extra register.
- What is infer latch means? How can you avoid it?
- How can you define strength in Verilog
- What is parameter overriding in Verilog
- Design divide-by-5 module.
- Write a Verilog code for 5:1 MUX
- Can you talk about the Verilog event scheduler?
- Difference between dual port ram and FIFO.
- What will be the output of x, y, z if c is the clock?
logic m = c;
reg n = c;
wire o = c;
Interview Questions