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The most frequently asked Verilog interview questions are listed below

Basic Level Questions

  1. Difference between blocking and non-blocking assignments
  2. Difference between task and function
  3. Difference between wire and reg
  4. What is generate block in Verilog and its usage?
  5. Difference between while and do-while loop
  6. What is an automatic keyword in the task?
  7. Difference between combination and sequential circuits.
  8. Difference between flip-flop and latch.
  9. Explain the difference between a static and automatic variable with example.
  10. Difference between Mealy and Moore FSM.
  11. Implement XOR gate using 2:1 MUX
  12. Implement OR gate using 2:1 MUX
  13. Difference between $stop and $finish.
  14. Design frequency/2 circuit using DFF.
  15. Difference between $random and $urandom

Intermediate level questions

  1. What is the default value of wire and reg?
  2. Explain inertial delay and transport delay.
  3. Difference between inter and intra assignment delay
  4. Difference between full and parallel case
  5. Difference between casex and casez
  6. Can you implement DFF in synchronous and asynchronous mode?
  7. What is #0 in Verilog and its usage?
  8. How to generate two different clocks in testbench?
  9. Implement flip-flop using 2:1 MUX
  10. Design overlapping and non-overlapping FSM for sequence detector 1010.
  11. Design Mod-3 counter and draw its waveform.
  12. Write a Verilog code for D-Latch.
  13. How can you override the existing parameter value?
  14. What is Synthesis?
  15. Write an RTL code to generate 60% duty cycle clock.
  16. Write an RTL code to generate 100MHz clock.
  17. Difference between `define and `include.
  18. What is force and release in Verilog?
  19. What will be output of the following code
always@(clock) begin
  a = 0;
  a <= 1;

Difficult level questions

  1. Why always block is not used inside a program block?
  2. What is FIFO and write Verilog code for the design?
  3. What will happen if there is no else part in if-else?
  4. Explain overflow and underflow in FIFO.
  5. What are all different applications of FIFO?
  6. Swap register content with and without using an extra register.
  7. What is infer latch means? How can you avoid it?
  8. How can you define strength in Verilog
  9. What is parameter overriding in Verilog
  10. Design divide-by-5 module.
  11. Write a Verilog code for 5:1 MUX
  12. Can you talk about the Verilog event scheduler?
  13. Difference between dual port ram and FIFO.
  14. What will be the output of x, y, z if c is the clock?
logic m = c;
reg n = c;
wire o = c;