Read and Write Transactions

SPI transactions are often described as reads or writes, but the wires are active in both directions whenever the controller provides clocks. The difference is which direction carries the meaningful payload.

Read Transactions

In a read transaction, the controller usually sends a command and address first. After that, it sends dummy bits so the peripheral has clock cycles to return data on MISO.

The dummy bits are not important as write data. They simply keep SCLK running so the peripheral can shift DATA_H and DATA_L back to the controller.

Write Transaction

In a write transaction, MOSI usually carries the meaningful command, address, and write data. MISO may be ignored, may carry dummy bits, or may return optional status depending on the peripheral.

Some SPI transactions are truly full duplex: both MOSI and MISO carry useful payload at the same time. This is common in streaming or shift-register-like use cases, but many register-style peripherals use command/address/dummy/data phases instead.

Transaction Type	What the Controller Sends on MOSI	What the Controller Receives on MISO
Write	Command, address, and write data	Often ignored, dummy, or optional status
Read	Command, address, then dummy bits	Data returned during the dummy/data phase
Full-duplex exchange	Meaningful transmit data	Meaningful receive data at the same time

The key point is that every receive bit still requires a clock. A read operation is therefore not passive; the controller actively clocks the bus and usually transmits dummy bits while collecting the returned data.

SPI Protocol