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SPI Introduction
SPI stands for Serial Peripheral Interface. It is a synchronous serial communication interface commonly used to connect a controller such as a microcontroller, processor, FPGA, or SoC block to nearby peripherals such as flash memories, ADCs, DACs, sensors, displays, codecs, and shift registers.
In baseline 4-wire SPI, one controller generates a serial clock and selects one peripheral using a chip-select signal. During the selected window, one bit is shifted from controller to peripheral and one bit is shifted from peripheral to controller on each serial clock cycle. That simultaneous shifting is why SPI is often described as full duplex.
The older names are master and slave. Many newer documents use controller/host and peripheral/target. This tutorial uses controller and peripheral, while mentioning legacy names where useful because datasheets still use them.
Why SPI Is Used
SPI is popular because it is simple, fast, and easy to implement in hardware.
| Feature | Why It Helps |
|---|---|
| Separate clock | The receiver does not need to recover timing from data. |
| Separate data directions | Full-duplex transfer is natural. |
| Dedicated chip select | Device selection is simple and deterministic. |
| No mandatory addressing phase | Peripheral-specific command formats are flexible. |
| Simple RTL | A shift register, clock divider, chip-select controller, and small FSM can implement many SPI controllers. |
SPI is usually used for short-distance communication on the same PCB or between tightly connected boards. It is not designed for long cables, hot plugging, automatic device discovery, or shared multi-controller arbitration in the generic baseline.
Terminology and Roles
| Term | Meaning |
|---|---|
| Controller, host, main, master | Device that normally initiates the transfer, drives SCLK, and controls CS/SS. |
| Peripheral, target, subnode, slave | Device selected by the controller. It responds while its chip select is active. |
| SCLK, SCK, CLK | Serial clock generated by the controller in the baseline bus. |
| MOSI, COPI, SDI | Controller output, peripheral input. |
| MISO, CIPO, SDO | Controller input, peripheral output. |
| CS, SS, nCS, nSS | Chip select or slave select. Often active low. |
| Word | A group of serial bits shifted as one programmed unit, commonly 8 bits but not required to be 8. |
| Transfer | One contiguous set of serial clock edges, usually while CS is asserted. |
| Transaction | A higher-level operation such as command plus address plus dummy cycles plus data. |
Note: SPI naming is not fully uniform. A peripheral datasheet may call MOSI by names such as DIN, SDI, or SI; it may call MISO by names such as DOUT, SDO, or SO. Always interpret names from the device’s point of view.
Signal Overview
Baseline 4-wire SPI uses these signals:
| Signal | Driven By | Typical Direction | Purpose |
|---|---|---|---|
| SCLK | Controller | Controller to all peripherals | Serial timing reference. |
| MOSI | Controller | Controller to selected peripheral | Command, address, write data, or dummy bits from controller. |
| MISO | Selected peripheral | Peripheral to controller | Read data, status, or dummy bits from peripheral. |
| CS/SS | Controller | One line per peripheral in common topology | Selects the active peripheral. Usually active low. |
When no peripheral is selected, inactive peripherals should not drive the shared MISO line. In RTL terms, each peripheral’s MISO output is either tri-stated at board level, multiplexed at SoC level, or otherwise prevented from contending.
Applications
SPI is widely used for:
- Serial NOR flash and EEPROM
- ADC and DAC devices
- Temperature, pressure, and motion sensors
- Display controllers
- Audio codecs
- Shift registers and GPIO expanders
- Touch controllers
- Secure elements
- FPGA configuration memories
SPI Protocol