Demultiplexer

A demultiplexer (DEMUX) is a combinational circuit that works exactly opposite to a multiplexer. A DEMUX has a single input line that connects to any one of the output lines based on its control input signal (or selection lines)

Usually, for ‘n’ selection lines, there are N = 2^n output lines.

Nomenclature: 1:N denotes one input line and ‘N’ output lines.

1:2 Demultiplexer

1:2 DEMUX has one select line and 2 output lines.

Block Diagram

Truth Table

1:2 Demux Verilog Code

module demux_2_1(
  input sel,
  input i,
  output y0, y1);
  
  assign {y0,y1} = sel?{1'b0,i}: {i,1'b0};
endmodule

Testbench Code

module demux_tb;
  reg sel, i;
  wire y0, y1;
  
  demux_2_1 demux(sel, i, y0, y1);
  initial begin
    $monitor("sel = %h: i = %h --> y0 = %h, y1 = %h", sel, i, y0, y1);
    sel=0; i=0; #1;
    sel=0; i=1; #1;
    sel=1; i=0; #1;
    sel=1; i=1; #1;
  end
endmodule

Output:

sel = 0: i = 0 --> y0 = 0, y1 = 0
sel = 0: i = 1 --> y0 = 1, y1 = 0
sel = 1: i = 0 --> y0 = 0, y1 = 0
sel = 1: i = 1 --> y0 = 0, y1 = 1

1:4 Demultiplexer

1:4 DEMUX has one select line and 4 output lines.

Block Diagram

Truth Table

1:4 Demux Verilog Code

module demux_1_4(
  input [1:0] sel,
  input  i,
  output reg y0,y1,y2,y3);
    
  always @(*) begin
    case(sel)
      2'h0: {y0,y1,y2,y3} = {i,3'b0};
      2'h1: {y0,y1,y2,y3} = {1'b0,i,2'b0};
      2'h2: {y0,y1,y2,y3} = {2'b0,i,1'b0};
      2'h3: {y0,y1,y2,y3} = {3'b0,i};
      default: $display("Invalid sel input");
    endcase
  end
endmodule

Testbench Code

module tb;
  reg [1:0] sel;
  reg i;
  wire y0,y1,y2,y3;
  
  demux_1_4 demux(sel, i, y0, y1, y2, y3);
  
  initial begin
    $monitor("sel = %b, i = %b -> y0 = %0b, y1 = %0b ,y2 = %0b, y3 = %0b", sel,i, y0,y1,y2,y3);
    sel=2'b00; i=0; #1;
    sel=2'b00; i=1; #1;
    sel=2'b01; i=0; #1;
    sel=2'b01; i=1; #1;
    sel=2'b10; i=0; #1;
    sel=2'b10; i=1; #1;
    sel=2'b11; i=0; #1;
    sel=2'b11; i=1; #1;
  end
endmodule

Output:

sel = 00, i = 0 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 0
sel = 00, i = 1 -> y0 = 1, y1 = 0 ,y2 = 0, y3 = 0
sel = 01, i = 0 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 0
sel = 01, i = 1 -> y0 = 0, y1 = 1 ,y2 = 0, y3 = 0
sel = 10, i = 0 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 0
sel = 10, i = 1 -> y0 = 0, y1 = 0 ,y2 = 1, y3 = 0
sel = 11, i = 0 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 0
sel = 11, i = 1 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 1

1:4 DEMUX using 1:2 DEMUXes

Block Diagram

1:4 DEMUX using 1:2 DEMUXes Verilog Code

module demux_2_1(
  input sel,
  input i,
  output y0, y1);
  
  assign {y0,y1} = sel?{1'b0,i}: {i,1'b0};
endmodule

module demux_1_4(
  input sel0, sel1,
  input  i,
  output reg y0, y1, y2, y3);
  
  wire z1,z2;
  
  demux_2_1 d1(sel0, i, z1, z2);
  demux_2_1 d2(sel1, z1, y0, y1);
  demux_2_1 d3(sel1, z2, y2, y3);
endmodule

Testbench Code

module tb;
  reg sel0, sel1;
  reg i;
  wire y0,y1,y2,y3;
  
  demux_1_4 demux(sel0, sel1, i, y0, y1, y2, y3);
  
  initial begin
    $monitor("sel0 = %b, sel1 = %b, i = %b -> y0 = %0b, y1 = %0b ,y2 = %0b, y3 = %0b", sel0, sel1, i, y0,y1,y2,y3);
    sel0=0; sel1=0; i=0; #1;
    sel0=0; sel1=0; i=1; #1;
    sel0=0; sel1=1; i=0; #1;
    sel0=0; sel1=1; i=1; #1;
    sel0=1; sel1=0; i=0; #1;
    sel0=1; sel1=0; i=1; #1;
    sel0=1; sel1=1; i=0; #1;
    sel0=1; sel1=1; i=1; #1;
  end
endmodule

Output:

sel0 = 0, sel1 = 0, i = 0 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 0
sel0 = 0, sel1 = 0, i = 1 -> y0 = 1, y1 = 0 ,y2 = 0, y3 = 0
sel0 = 0, sel1 = 1, i = 0 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 0
sel0 = 0, sel1 = 1, i = 1 -> y0 = 0, y1 = 1 ,y2 = 0, y3 = 0
sel0 = 1, sel1 = 0, i = 0 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 0
sel0 = 1, sel1 = 0, i = 1 -> y0 = 0, y1 = 0 ,y2 = 1, y3 = 0
sel0 = 1, sel1 = 1, i = 0 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 0
sel0 = 1, sel1 = 1, i = 1 -> y0 = 0, y1 = 0 ,y2 = 0, y3 = 1

Verilog Codes