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The most frequently asked SystemVerilog interview questions are listed below

Basic Level Questions

  1. Difference between byte a and bit [7:0] a
  2. Why logic is introduced in SV? Or Why reg and wires are not sufficient?
  3. Difference between reg and logic?
  4. What are 2 state and 4 state variables? Provide some examples.
  5. Difference between integer and int
  6. Difference between packed and unpacked arrays
  7. Difference between dynamic and associative arrays
  8. Difference between dynamic array and queue
  9. Difference between structure and union
  10. Difference between while and do while questions
  11. Difference between function and task
  12. What are pass-by-value and pass-by-reference methods?
  13. Why do we need randomization in SystemVerilog?
  14. Difference between module and program block?
  15. How do program block avoid the race condition?
  16. Difference between === and == operators?
  17. What are SystemVerilog interfaces and why are they introduced?
  18. What is modport and clocking block?
  19. What is the final block? Difference between initial and final block.
  20. What is cross-coverage?
  21. Difference between code and functional coverage?
  22. Different types of code coverage.

Intermediate level questions

  1. How to find indexes associated with associative array items?
  2. Difference between fork-join, fork-join_any, and fork-join_none
  3. Difference Between Always_comb and Always@(*)?
  4. Difference between structure and class
  5. Difference between static and automatic variables
  6. Difference between static and automatic methods in classes
  7. Difference between new[ ] and new() ?
  8. Difference between shallow and deep copy
  9. How does the OOP concept add benefit in Verification?
  10. What is inheritance?
  11. What are the ‘super’ and ‘this’  keywords in SystemVerilog?
  12. What is polymorphism and its advantages?
  13. What is virtual function?
  14. What is the use of scope resolution operator?
  15. Difference between virtual and pure virtual function
  16. What is a virtual interface and its need?
  17. What is virtual class?
  18. What are parameterized classes?
  19. Difference between rand and randc?
  20. Difference between pre_randomize and post_randomize
  21. Explain bidirectional constraints
  22. Is it possible to override existing constraints?
  23. Difference between :/ and := operators in randomization
  24. What is std::randomize?
  25. Is it possible to call a function from constraint? If yes, explain with an example.
  26. Write a constraint for the 8-bit variable that provides distribution 70% for range 0-100 and the remaining 30% for range 101-255.
  27. Derive odd numbers within the range of 10 to 30 using SV constraint.
  28. Write a constraint – divisible by 5.
  29. Write a constraint to detect odd numbers of 1’s in an 8-bit sequence.
  30. How to disable constraints?
  31. How to disable randomization?
  32. What is `timescale?
  33. Difference between static and dynamic casting
  34. Difference between mailbox and queue
  35. What is semaphore and in what scenario is it used?
  36. What is input and output skew in clocking block?
  37. What are the types of assertions?
  38. Difference between $strobe, $monitor and $display
  39. What is ignore bins?
  40. Difference between ignore and illegal bins.
  41. How do you define callback?
  42. What is DPI? Explain DPI export and import.
  43. What is pass by value and pass by reference in SystemVerilog?
  44. What is the implication operator in SVA? Explain its type?
  45. What all bins are generated by the following code
coverpoint addr {bins b1 = {1, 10, 12};
                 bins b2[] = {[2:9], 11};
                       bins b3[4] = {0:8};

Difficult level questions

  1. What are the default values of variables in the SystemVerilog constructor?
  2. What are local and protected access qualifiers?
  3. How do you implement the randc function in SystemVerilog?
  4. Is it possible to generate random numbers without using rand or randc keywords?
  5. Difference between @posedge and $rose?
  6. How will you make sure that address ranges from 0x2000 to 0x9000 is covered?
  7. Talk about basic testbench components.
  8. Explain the cycle of verification and its closure.
  9. How will you test the functionality of interrupts using functional coverage?
  10. What is layered architecture in Verification?
  11. How can you establish communication between monitor and scoreboard in SystemVerilog?
  12. Difference between class-based testbench and module-based testbench.
  13. How will be your approach if code coverage is 100% but functional coverage is too low?
  14. How will be your approach if functional coverage is 100% but code coverage is too low?
  15. Write an assertion for glitch detection.