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SystemVerilog Interview Questions
The most frequently asked SystemVerilog interview questions are listed below
Basic Level Questions
- Difference between byte a and bit [7:0] a
- Why logic is introduced in SV? Or Why reg and wires are not sufficient?
- Difference between reg and logic?
- What are 2 state and 4 state variables? Provide some examples.
- Difference between integer and int
- Difference between packed and unpacked arrays
- Difference between dynamic and associative arrays
- Difference between dynamic array and queue
- Difference between structure and union
- Difference between while and do while questions
- Difference between function and task
- What are pass-by-value and pass-by-reference methods?
- Why do we need randomization in SystemVerilog?
- Difference between module and program block?
- How do program block avoid the race condition?
- Difference between === and == operators?
- What are SystemVerilog interfaces and why are they introduced?
- What is modport and clocking block?
- What is the final block? Difference between initial and final block.
- What is cross-coverage?
- Difference between code and functional coverage?
- Different types of code coverage.
Intermediate level questions
- How to find indexes associated with associative array items?
- Difference between fork-join, fork-join_any, and fork-join_none
- Difference Between Always_comb and Always@(*)?
- Difference between structure and class
- Difference between static and automatic variables
- Difference between static and automatic methods in classes
- Difference between new[ ] and new() ?
- Difference between shallow and deep copy
- How does the OOP concept add benefit in Verification?
- What is inheritance?
- What are the ‘super’ and ‘this’ keywords in SystemVerilog?
- What is polymorphism and its advantages?
- What is virtual function?
- What is the use of scope resolution operator?
- Difference between virtual and pure virtual function
- What is a virtual interface and its need?
- What is virtual class?
- What are parameterized classes?
- Difference between rand and randc?
- Difference between pre_randomize and post_randomize
- Explain bidirectional constraints
- Is it possible to override existing constraints?
- Difference between :/ and := operators in randomization
- What is std::randomize?
- Is it possible to call a function from constraint? If yes, explain with an example.
- Write a constraint for the 8-bit variable that provides distribution 70% for range 0-100 and the remaining 30% for range 101-255.
- Derive odd numbers within the range of 10 to 30 using SV constraint.
- Write a constraint – divisible by 5.
- Write a constraint to detect odd numbers of 1’s in an 8-bit sequence.
- How to disable constraints?
- How to disable randomization?
- What is `timescale?
- Difference between static and dynamic casting
- Difference between mailbox and queue
- What is semaphore and in what scenario is it used?
- What is input and output skew in clocking block?
- What are the types of assertions?
- Difference between $strobe, $monitor and $display
- What is ignore bins?
- Difference between ignore and illegal bins.
- How do you define callback?
- What is DPI? Explain DPI export and import.
- What is pass by value and pass by reference in SystemVerilog?
- What is the implication operator in SVA? Explain its type?
- What all bins are generated by the following code
coverpoint addr {bins b1 = {1, 10, 12};
bins b2[] = {[2:9], 11};
bins b3[4] = {0:8};
Difficult level questions
- What are the default values of variables in the SystemVerilog constructor?
- What are local and protected access qualifiers?
- How do you implement the randc function in SystemVerilog?
- Is it possible to generate random numbers without using rand or randc keywords?
- Difference between @posedge and $rose?
- How will you make sure that address ranges from 0x2000 to 0x9000 is covered?
- Talk about basic testbench components.
- Explain the cycle of verification and its closure.
- How will you test the functionality of interrupts using functional coverage?
- What is layered architecture in Verification?
- How can you establish communication between monitor and scoreboard in SystemVerilog?
- Difference between class-based testbench and module-based testbench.
- How will be your approach if code coverage is 100% but functional coverage is too low?
- How will be your approach if functional coverage is 100% but code coverage is too low?
- Write an assertion for glitch detection.
Interview Questions