AXI Introduction
AXI is part of the AMBA family of on-chip protocols. It targets high-bandwidth, low-latency, high-frequency SoC communication. Compared with simpler bus protocols, AXI separates address, data, and response movement into independent channels. This lets a design pipeline traffic, add register stages, accept multiple outstanding requests, and complete transactions out of order when ordering rules permit it.
The AXI specification defines the interface contract. It does not define a particular memory controller, interconnect implementation, cache design, or register map. A Manager can be a CPU interface, DMA engine, accelerator, debug block, PCIe bridge, or another protocol bridge. A Subordinate can be memory, a peripheral, a bridge, an SMMU, a cache, or another system block. The Interconnect connects them and preserves the protocol rules while routing traffic.
AXI is usually chosen when APB is too simple and AHB-style single address/data pipeline behavior is not enough. AHB is a pipelined bus with an address phase and a data phase. AXI goes further by making read and write paths independent, supporting multiple outstanding transactions, and using IDs to match responses back to requests.
AXI components
| Term | Meaning |
|---|---|
| Manager | Component that initiates AXI transactions. It drives requests and write data, and receives read data and write responses. |
| Subordinate | Component that accepts AXI requests and returns responses. It receives write data and produces read data. |
| Interconnect | Routing and arbitration fabric that connects Manager and Subordinate interfaces. |
| Interface | A set of AXI channel transmitters and receivers on a component. |
| Channel | A unidirectional path for transfers, such as AW, W, B, AR, R, AC, or CR. |
| Transfer | One cycle of communication on a channel. |
| Transaction | The full set of transfers needed to perform an operation, such as one read request plus one or more read data transfers. |
- A Manager issues a request on
AWfor writes orARfor reads. - Write data travels on
W; read data returns onR. - Write completion returns on
B; read responses ride with eachRdata beat. - Every channel has its own transfer handshake or credit mechanism.
- IDs allow multiple transactions to be outstanding and responses to be matched back to the correct request.
- Attributes tell the system whether the request is cacheable, bufferable, shareable, protected, translated, tagged, or otherwise special.
AXI Protocol