Request Attributes

AXI request attributes tell the downstream system how to treat the transaction. These attributes affect buffering, cache lookup, cache allocation, protection, physical address space, encryption context, region decode, and QoS.

Before the detailed tables, keep this term map in mind:

Term	Meaning
Downstream system	The interconnect, cache, memory controller, bridge, or endpoint that receives the request after the Manager issues it.
Attribute	Extra request information that tells downstream logic how the transaction is allowed to behave. The address says where; the attributes say how.
Buffering	Allowing an intermediate component to accept a write and respond before the final endpoint has completed the write.
Cache lookup	Checking whether data is already present in a cache instead of always going to final memory.
Cache allocation	Allowing a cache to create a new cache entry for the transaction.
Modifiable	Allows permitted interconnect transformations such as splitting, merging, widening, or changing selected attributes.
Non-modifiable	Keeps the key transaction properties fixed so the request behaves like a direct access.
Shareability	Describes whether other agents or caches can share the memory location and therefore whether coherency rules matter.
Protection	Describes privilege, instruction/data intent, and physical address space.
Physical address space	A security or isolation category for the physical address, such as Secure, Non-secure, Root, or Realm.
Region	Extra decode information for multiple logical regions behind one interface.
QoS	Quality of Service. A priority hint used by arbitration and scheduling logic.

Subordinate types

The specification distinguishes Memory Subordinates from Peripheral Subordinates.

Subordinate type	Protocol expectation
Memory Subordinate	Required to handle all transaction types correctly.
Peripheral Subordinate	Has an implementation-defined access method, usually described in the component documentation. Unsupported accesses must complete in a protocol-compliant manner, but correct peripheral operation after such accesses is not guaranteed.

This distinction matters because transactions that are legal for memory can be unsafe for a peripheral. For example, a Modifiable transaction can be split, merged, or transformed by interconnect logic. That is usually inappropriate for a peripheral register access.

Memory attributes

AWCACHE and ARCACHE, collectively called AxCACHE, describe memory behavior. The bits are:

Bit	Meaning
`AxCACHE[0]`	Bufferable
`AxCACHE[1]`	Modifiable
`AxCACHE[2]` and `AxCACHE[3]`	Allocate and Other Allocate hints. The read/write bit positions differ for Allocate and Other Allocate.

Bufferable affects when a write response can be returned and where read data can be sourced. Modifiable affects whether a transaction can be split, merged, resized, or otherwise transformed.

Modifiable, AxCACHE[1]

A Non-modifiable transaction must not be split or merged with other transactions. Its address, size, length, burst type, and protection attributes are fixed. AxCACHE can only be changed in a limited way to convert Bufferable to Non-bufferable. IDs and QoS values can be changed.

A Modifiable transaction can be split, merged, widened, or otherwise transformed, but not in a way that violates visibility, address-space, cache lookup, or atomicity requirements. An interconnect can fetch more data for a read, or perform a larger write with WSTRB limiting which bytes are updated.

The key design rule is simple: use Non-modifiable behavior for Device/peripheral-like operations, and use Modifiable behavior where memory-system optimization is permitted.

Memory types

The combination of AxCACHE bits defines memory type. The most important categories are:

Memory type	Key behavior
Device Non-bufferable	Write response and read data come from final destination. Non-modifiable. No prefetch. No write merging.
Device Bufferable	Write response can come from an intermediate point, but write must reach final destination in a timely manner. Reads come from final destination. Non-modifiable.
Normal Non-cacheable Non-bufferable	Write response and read data come from final destination. Modifiable. Write merging is allowed.
Normal Non-cacheable Bufferable	Write response can be intermediate. Reads can come from final destination or a progressing write. Modifiable.
Write-Through	Write must become visible at final destination in a timely manner. Reads can come from cached copies. Cache lookup required.
Write-Back	Write is not required to become visible at final destination immediately. Reads can come from cached copies. Cache lookup required.

Mismatched cacheability or shareability attributes for the same memory region can cause software protocol errors. A system must not deadlock because of such an error, but coherency and data correctness can be lost. A hardware protocol error, by contrast, has no required recovery behavior.

Protection attributes

Protection attributes identify privilege, instruction/data intent, and physical address space.

Signal group	Meaning
`AxPROT`	Traditional protection attributes.
`AxNSE`	Extends `AxPROT[1]` when RME is used.
`AxPRIV`	Privileged or unprivileged access. Supersedes `AxPROT[0]` when present.
`AxINST`	Instruction or data access. Supersedes `AxPROT[2]` when present.
`AxPAS`	Physical Address Space. Supersedes `AxPROT/AxNSE` PAS encoding when present.

An interface must not include both AxPAS and the AxPROT/AxNSE PAS signaling form. If PROT_Present is True, PAS_WIDTH must be zero and INSTPRIV_Present must be False.

Physical address spaces include Secure, Non-secure, Root, Realm, System Agent, and Non-secure Protected. Root and Realm are associated with RME. System Agent and Non-secure Protected are associated with GDI.

Realm Management Extension

Realm Management Extension extends memory protection by adding Root and Realm physical address spaces.

Granular Data Isolation

Granular Data Isolation adds the System Agent and Non-secure Protected physical address spaces. If GDI is supported, RME must also be supported, PAS_WIDTH must be 3, and untranslated transaction support must be either absent or version 4.

Memory Encryption Contexts

Memory Encryption Contexts associate Realm, System Agent, or Non-secure Protected accesses with a memory encryption context ID. AxMECID is present when MEC is supported. Secure, Non-secure, and Root physical address spaces must use MECID zero. Realm, System Agent, and Non-secure Protected accesses can use MECID values when supported.

Caches that store data associated with MECID must preserve that MECID and provide it on write-back. For GDI address spaces, MECID mismatch behavior must not leak confidential data.

Multiple region interfaces

AxREGION is a 4-bit region identifier used downstream of an address decode function. It can identify up to 16 logical regions behind one physical interface. It does not create a new independent address space; it is additional decode information.

QoS signaling

AxQOS is a 4-bit Quality of Service identifier. The protocol recommends treating higher values as higher priority, but the exact system-level policy is implementation-defined. AXI ordering rules take precedence over QoS. Optional VAWQOSACCEPT and VARQOSACCEPT signals let a Subordinate indicate the minimum QoS value it accepts without significant delay.

AXI Protocol