Cache
AXI cache behavior is controlled by memory type, shareability, domain, opcode, and optional feature support. The specification uses the term cache broadly for intermediate storage structures, including caches and buffers.
Think of AXI caching as a visibility problem. A cached copy can improve performance, but the system must still define which agents are allowed to see that copy, who is responsible for writing Dirty data back, and which requests must look in peer or in-line caches before going to memory.
Caching in AXI
AXI cache behavior is controlled by request attributes, Domain, opcode, and feature properties. A cache or buffer must preserve the required visibility and ordering behavior for the memory type it accepts.
Three common coherency styles appear in AXI-based systems:
| Style | How stale data is avoided |
|---|---|
| Non-cacheable access | The request is not stored in local caches, so later observers do not see an old cached copy. |
| Software coherency | Software or firmware performs cache maintenance at ownership handoff points. |
| Hardware coherency | A coherent interconnect snoops or checks relevant caches automatically. |
Cache line size
The Cache_Line_Size property indicates cache line size. Many cache-related opcodes require cache-line-sized and Regular transactions. Cache line size becomes important for wrapping bursts, cache maintenance, prefetching, stashing, MTE tag granularity, and read data chunking.
For cache-line-sized transactions, the total transfer size must match the cache line size. For writes with data, byte strobes must cover the complete cache-line container. This is why full-line opcodes such as WriteNoSnoopFull, WriteUniqueFull, WriteBackFull, WriteEvictFull, WriteZero, and several CMO/stash opcodes are stricter than ordinary reads or writes.
Cache coherency and Domains
AxDOMAIN identifies the shareability domain of a request:
| Domain | Typical meaning |
|---|---|
| Non-shareable | Caches local to the issuing component are involved. Other agents are not expected to share the line coherently. |
| Shareable | Peer and in-line caches can be involved. Coherency behavior matters. |
| System | System-level operations such as some Device or ACT use cases. |
Legal combinations of memory type and Domain determine which caches must be accessed. A request to cacheable Shareable memory can require peer cache and in-line cache lookup. A Non-cacheable Non-shareable request usually does not require cache lookup.
Domain consistency is just as important as the domain value itself. If one Manager treats a location as Non-shareable and another treats the same location as Shareable, cached Non-shareable data must be made visible before the Shareable agent uses it. Otherwise the protocol cannot magically recover coherency from inconsistent system attributes.
I/O coherency
I/O coherent AXI Managers can interact with coherent parts of the system without directly using a full coherent processor protocol. For example, an I/O agent can issue requests that cause coherent cache lookup or stashing so data appears closer to the consumer.
Some AXI configurations support caching Shareable lines in system caches or other shared caches. This allows data that is shared across agents to remain in a cache structure while preserving the rules about which requests can hit, clean, invalidate, or take ownership of that line.
Prefetch transaction
Prefetch transactions are hints. They request that data be fetched before a later demand access. The read response PREFETCHED indicates that read data is valid and came from a prefetched source. A PREFETCHED response cannot be sent for an exclusive read and requires a wider RRESP configuration.
Cache Stashing
Cache stashing lets one component indicate that data should be placed in another cache. Stashing is a hint: a cache or system component can ignore the stash portion of a request. Stash transactions include write-with-stash and data-less stash forms, and can optionally include Node ID and Logical Processor ID target fields.
Deallocating read transactions
Deallocating read transactions such as ReadOnceCleanInvalid and ReadOnceMakeInvalid tell the system that the data is not likely to be used again.
Invalidate hint
InvalidateHint is a data-less hint that the line can be invalidated when no longer needed. These operations are not substitutes for required cache maintenance when correctness depends on visibility.
AXI Protocol