APB Protocol

Introduction

AMBA APB, or Advanced Peripheral Bus, is a simple synchronous bus protocol used for low-bandwidth peripheral register access inside SoCs. It is optimized for low cost, low power, and small interface complexity rather than high throughput. In a typical AMBA system, a higher-performance bus such as AXI or AHB connects to an APB bridge, and the bridge performs APB transfers to peripherals such as timers, GPIO blocks, UARTs, interrupt controllers, configuration registers, and power-management blocks.

This tutorial uses Requester and Completer terminology, matching the AMBA APB Protocol Specification. The APB bridge is the Requester because it initiates APB transfers. The peripheral is the Completer because it responds to the selected transfer.

The History and Evolution of APB Protocol

The Advanced Peripheral Bus (APB) is maintained by Arm and has evolved over the decades alongside the broader Advanced Microcontroller Bus Architecture (AMBA) standards. As System-on-Chip (SoC) designs became more complex, APB was incrementally updated to support new power, security, and timing requirements without losing its core simplicity.

Here is the chronological history of the APB protocol:

  • AMBA 1 (1995): Arm introduced the first generation of AMBA, which included the Advanced System Bus (ASB) and the original Advanced Peripheral Bus (APB). From the very beginning, APB was designed as a basic, unpipelined interface meant to strip away unnecessary complexity for low-speed peripherals.

  • AMBA 2 (1999): Often referred to informally as APB2, this version was released alongside the Advanced High-performance Bus (AHB). It formalized the standard APB interface that many foundational IP blocks were built upon. However, it was strictly rigid—there was no native support for wait states or error signaling.

  • AMBA 3 (2003) – Introduction of APB3: Released in conjunction with the powerful AXI protocol, APB3 added much-needed flexibility for peripherals operating at different speeds. It introduced two critical signals:

    • PREADY: Allowed slower Completer peripherals to insert wait states to extend transfers.

    • PSLVERR: Enabled basic error reporting if a transfer failed.

  • AMBA 4 (2010) – Introduction of APB4: Launched alongside AXI4, APB4 added features necessary for secure and data-specific SoC architectures. The updates included:

    • PPROT: A protection signal to support both secure and non-secure transactions, as well as instruction vs. data accesses.

    • PSTRB: Write strobe signals to enable sparse data transfers (byte-enable granularity) on the write data bus.

  • AMBA 5 (2014 & Beyond) – APB5 Updates: As the AMBA 5 generation rolled out (introducing CHI and AXI5), the APB specification received further enhancements to align with highly advanced, power-sensitive designs. Modern updates introduced PWAKE (wake-up signaling) and user-defined pins, integrating APB more tightly with system-wide low-power interfaces like Q-Channel and P-Channel.

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