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APB is part of the AMBA family of on-chip bus protocols. Its job is not to move large data streams at high bandwidth. Its job is to provide a clean, low-complexity path to peripheral registers.

The APB protocol is:

  1. Synchronous: all protocol signals are timed against the rising edge of PCLK.
  2. Simple: the transfer sequence is based on a Setup phase followed by an Access phase.
  3. Non-pipelined: a transfer must complete before the next APB transfer can complete.
  4. Low cost: APB avoids the complexity of burst, out-of-order, and multi-channel protocols.
  5. Peripheral-oriented: it is normally used for control and status registers rather than large memory traffic.

The AMBA APB specification states that every APB transfer takes at least two cycles. This is the core mental model for APB: one cycle to set up the transfer, and one or more cycles to access the selected peripheral.

Why APB is used

APB is useful when an SoC needs many small register interfaces. A high-performance bus can be expensive to route into every small peripheral. Instead, an APB bridge can convert a system-level transaction into a simpler APB access.

Common APB-connected blocks include:

  • Timers and watchdogs
  • GPIO controllers
  • UART, SPI, and I2C configuration registers
  • Interrupt controller registers
  • Reset and clock control registers
  • Power-management registers
  • Debug and trace control registers
  • Small status/control blocks inside larger IP

APB advantages

  1. It has a small signal set for the baseline protocol.
  2. Its two-phase transfer is easy to implement in RTL.
  3. It is suitable for low-frequency and low-power peripheral regions.
  4. It supports wait states using PREADY.
  5. It supports error response using PSLVERR in APB3 and later.
  6. It supports byte-lane writes and protection attributes in APB4 and later.
  7. APB5 adds optional wake-up, user, RME, and parity-related features.

APB limitations

  1. It is not pipelined.
  2. It does not support bursts.
  3. It is not intended for high-throughput memory traffic.
  4. Read and write data buses exist separately, but APB does not perform concurrent read and write transfers.
  5. Performance depends on peripheral latency and wait-state behavior.
  6. Optional feature compatibility must be checked when connecting different APB revisions or interface configurations.

APB Protocol