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Read Transfers
In a read transfer, PWRITE is LOW. The Requester drives address and control. The selected Completer drives PRDATA before the read transfer completes.
With no wait states
The control timing is the same as a write transfer:
- Setup asserts PSEL.
- PENABLE is LOW during Setup.
- Access asserts PENABLE.
- With PREADY HIGH, the read completes at the next rising edge.
- PRDATA must be valid before the transfer completes.
with wait states
PREADY is the APB wait-state signal. It is driven by the Completer and sampled during the Access phase.
PREADY can extend both read and write transfers. When PENABLE is LOW, PREADY can take any value. This is why fixed-latency peripherals can tie PREADY HIGH.
How wait states work
| Access cycle condition | Meaning |
|---|---|
| PSEL=1, PENABLE=1, PREADY=0 | Transfer is still waiting. Hold stable signals. |
| PSEL=1, PENABLE=1, PREADY=1 | Transfer completes on this rising clock edge. |
| PENABLE=0 | PREADY is not used to complete a transfer. |
Stability rule
During wait states, the Requester must not change the active transfer. A common RTL bug is to update PADDR, PWDATA, or PSTRB while PREADY is still LOW. That can cause the Completer to accept a different transfer than the one that was originally set up.
Back-to-back transfers
After a completed Access phase, APB can go:
- Back to IDLE, if no more transfer is needed.
- Directly to a new SETUP, if another transfer follows.
Even in back-to-back operation, each transfer still has its own Setup cycle. PENABLE must be LOW in Setup.
APB Protocol