APB Architecture

In a typical SoC, the APB side is reached through a bridge. The bridge receives a transaction from a higher-performance interconnect, decodes the target address, selects one APB peripheral, and drives the APB transfer sequence.

The bridge is the Requester. It drives request-side signals such as address, select, enable, direction, write data, strobe, and protection attributes. The selected peripheral is the Completer. It returns read data, ready, error, and optional response/user information.

The important architectural idea is selection. APB uses a PSELx signal per Completer. A shared address/control/data path can be routed to many peripherals, but only the selected Completer participates in the active transfer.

Requester and Completer

Role	Common implementation	Main responsibility
Requester	APB bridge, bus adapter, local controller	Starts transfers, drives address/control/write data, asserts PSELx and PENABLE
Completer	APB peripheral register block	Accepts writes, returns read data, controls PREADY, optionally reports PSLVERR

Older material may use master/slave terminology. This tutorial uses Requester/Completer because that is the terminology used by the current APB specification.

APB bridge behavior

The APB bridge commonly performs these steps:

Accept a request from AXI, AHB, or a local internal bus.
Decode the address to choose the APB Completer.
Assert the correct PSELx.
Drive address, direction, write data, and attributes.
Assert PENABLE in the Access phase.
Wait for PREADY if the Completer needs extra cycles.
Return read data or error status to the upstream bus.

APB itself does not define the upstream bus. AXI-to-APB and AHB-to-APB bridges are common implementation choices, but APB remains the simple peripheral-side protocol.

APB Protocol