Error Response

PSLVERR is an optional APB3-and-later error response signal driven by the Completer. It can be used for both read and write transfers.

PSLVERR is only considered valid during the last cycle of an APB transfer, when PSEL, PENABLE, and
PREADY are all HIGH.
It is recommended, but not required, that PSLVERR is driven LOW when PSEL, PENABLE, or PREADY are
LOW.

PSLVERR is valid only in the final Access cycle:

pslverr_valid = PSEL && PENABLE && PREADY;

Write error behavior

If a write transfer completes with PSLVERR HIGH, it indicates an error response. However, this does not automatically mean that the target register was not updated. The effect of a failing write is peripheral-specific.

For example, an implementation might:

Reject the write and leave state unchanged.
Partially update internal state before detecting the error.
Update the register and still report an error for another reason.

The APB protocol allows these implementation-specific outcomes. Software and verification must use the peripheral specification to know the intended behavior.

Read error behavior

If a read transfer completes with PSLVERR HIGH, the read data may be invalid. There is no generic APB requirement that the Completer drive PRDATA to zero on an error. A Requester may still observe whatever value is present on PRDATA.

Mapping of PSLVERR

When an APB bridge reports an upstream error:

Bridge direction	Typical mapping
AXI to APB	APB PSLVERR maps to AXI RRESP for reads and BRESP for writes
AHB to APB	APB PSLVERR maps to AHB HRESP

APB Protocol