Data Types in Verilog
A storage format having a specific range or type is called data type. They can be divided into two groups.
- Net type group: The net-type group represents physical connections between digital circuits. Ex. wire, wand, wor, etc.
- Variable type group: The variable type group represents the storage of values in digital circuits. They are used as variables. Ex. reg, integer
Verilog supports 4 types of logic values as
|1||Logic one, true condition|
|0||Logic zero, false condition|
Nets represent physical connections between the digital circuits. They are declared using keyword wire. The term net is not a keyword, it is a group of data types such as wire, wand, wor, tri, etc.
wire a; //one-bit value as a single net. wire [5:0] a; //net as a vector
- The net and wire terms are interchangeably used.
- Usually, the default value of the net is z.
The registers represent data storage elements. It retains value till it is overridden. The registers are like a placeholder, so they do not require a driver. Keyword used to declare a register data type is reg.
reg a; // single bit register reg [5:0] a; // 6 bit register as a vector
- Registers are similar to variables in the C language.
- The default value of the reg is x.
Scalars and Vectors
Scalars: Single bit wire or register is known as a scalar.
wire a; reg a;
Vectors: The nets or registers can be declared as vectors to represent multiple bit widths. If bit width is not specified, it is a scalar.
wire [5:0] a; reg [5:0] a;
The value of constants can not be changed. It is read-only in nature.
Integer data type
The integers are general-purpose 32-bit register data types. They are declared by the ‘integer’ keyword.
The real data types can be constants or real register data types. They are declared using the ‘real’ keyword.
The real value is rounded off if they are assigned to integer data type,
real data = 3.14;
An ordered collection of characters is called a string. They can be stored in reg data type. Each character in a string requires 1 byte (8 bits) for storage and is typically mentioned within double-quotes (” “).
reg [8*11:0] name = "Hello World"; // String "Hello World" //requires 11 bytes space.
Verilog provides a time register to store simulation time. A time register is declared using the ‘time’ keyword and it has a width of at least 64 bits depending on the simulator and machine used.
time curr_time; // curr_time is a time variable.
Verilog allows arrays of reg, time, integer, and vector register data types.
integer count [0:5]; count // To access 2nd element in an array integer two_D_arr [3:0][3:0]; // illegal time timestamp[1:5]; // array of 5 timestamp variables. reg [3:0] var[0:7]; // Array of 8 var and each var has 4 as bit width
- Verilog does not allow the use of multidimensional arrays.
- Arrays for real variables are also not allowed in Verilog.
Verilog provides a facility to model register memories like ROM or RAM as an array of registers. Each array element in an array is called a word.
reg mem [0:511]; // Memory mem with 512 1-bit word. reg [3:0] mem [0:511]; // Memory mem with 512 4-bit words