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Lexical Conventions

The lexical tokens used in Verilog and C language are similar. They are specified as numbers, strings, identifiers, comments, delimiters, and keywords.

Numbers

The numbers can be specified in two ways

Types	Syntax	Description
sized	<size>'<base_format><number>	Size is explicitly specified
unsized	‘<base_format><number>	Size is not specified, depending on the simulator and machine it has the default number of bits. (Usually 32 bits)

Where, denotes

‘D or ‘d – Decimal format

‘B or ‘b – Binary format

‘H or ‘h – Hexadecimal format

‘O or ‘o – Octal format

Note:

In case of unsized numbers, if base_format is not specified, then it is treated as a decimal format.
Verilog provides two symbols ‘x’ to denote ‘unknown value’, and ‘z’ to denote ‘high impedance value’.
The underscore is used to separate bits for readability.
Negative numbers can be specified by using a minus sign before the size of a number and it is stored as 2’s complement of the number. It is illegal to use minus sign between <base_format> and <number>.
Example: -8’d5 (valid format and it is stored as 2’s complement of 5), 8’d-5 (Invalid format).

Examples:

sized	unsized
8’d7 (8-bit decimal number)	‘d56 (32-bit decimal number)
20’hab_561d (20-bit hexadecimal number)	’h48fa (32-bit hexadecimal number)
3’b101 (3-bit binary number)	‘o7a (32-bit octal number)

Comments

The comments are used for documentation and to describe any functionality in simple language.

Two ways to write comments

Comment types	Description
Single line comment	Single line comment starts with //
Multiple lines comment	Multiple lines can be enclosed as comments within /* and */. Multiple lines can not be nested.

Examples:

Single line comment

// This is a single-line comment

Multiple line comment

/* This is the first line.
This is the second line.
This is the third line.
...
*/

Whitespace

Verilog whitespace includes blank space(\b), tabs(\t) and newline(\n). They are ignored by Verilog except when it separates the tokens. They are not ignored in the strings. They are used for code indentation as well.

Example:

module tb;
  reg [1:0] data; // observe spaces are given for indentation.
  initial begin
    $display("Hello\tWorld"); // \t is used between 'Hello' and 'World'.
  end
endmodule

Operators

Verilog has three operator types: Unary, binary, and ternary

Operators	Description	Example
Unary	Appear before the operand.	Y = ~x;
Binary	Appear between two operands.	Y = x \|\| y
Ternary	Two separate operators appear to separate three operands	Z = (a < b)?x:y;

Operators are explained in detail in the Verilog operators section.

Strings

A string is a set of characters that are typically mentioned within double-quotes (” “). Each character in a string requires 1 byte to store. They can not be divided into multiple lines.

Example:

"Hello World" // Requires 11 bytes to store 11 characters.

Identifiers

The identifiers are the names given to the objects that can be referenced in the design.

They are case-sensitive and made up of alphanumeric characters (A to Z, a to z, 0 to 9), the underscore ( _ ), and the dollar sign ($).
They can not start with the dollar sign ($), and numbers.
Escaped identifiers begin with backslash \ character and end with whitespace (tab, space, or newline). They are meant to process literally. Example: \x+y

Examples

value_1  //Valid
$value_1 // Invalid
1_value // Invalid

Keywords

The keywords are special identifiers that are reserved to define the Verilog language construct. They are in lowercase.

Examples: module, endmodule, initial, always, begin, end, case, wire, while, etc.