Verilog blocks
The Verilog blocks are nothing but a group of statements that acts as one. The multiple statements are grouped together using ‘begin’ and ‘end’ keywords. Verilog classifies blocks into two types.
- Sequential blocks
- Parallel blocks
Sequential blocks |
Parallel blocks |
The sequential block executes a group of statements (blocking assignment statement) in a sequential manner in which they are specified. |
The parallel block executes a group of statements concurrently as their execution starts at the same simulation time. |
Keywords used: begin and end |
Keywords used: fork and join |
Example:
module tb;
reg [3:0] i1, i2, i3;
reg [3:0] x1, x2, x3;
// sequential block
initial begin
$monitor("T = %0t: i1 = %0d, i2 = %0d, i3 = %0d, x1 = %0d, x2 = %0d, x3 = %0d", $time, i1, i2, i3, x1, x2, x3);
i1 = 3;
i2 = 2;
#4 i3 = 7;
end
initial begin
#10;
// Parallel block
fork
x1 = i1;
#2 x2 = i2;
#5 x3 = i3;
join
#15 x1 = i1 + i2;
end
endmodule
Output:
T = 0: i1 = 3, i2 = 2, i3 = x, x1 = x, x2 = x, x3 = x
T = 4: i1 = 3, i2 = 2, i3 = 7, x1 = x, x2 = x, x3 = x
T = 10: i1 = 3, i2 = 2, i3 = 7, x1 = 3, x2 = x, x3 = x
T = 12: i1 = 3, i2 = 2, i3 = 7, x1 = 3, x2 = 2, x3 = x
T = 15: i1 = 3, i2 = 2, i3 = 7, x1 = 3, x2 = 2, x3 = 7
T = 30: i1 = 3, i2 = 2, i3 = 7, x1 = 5, x2 = 2, x3 = 7
Named blocks, and disabling named blocks
Both sequential and parallel blocks can be named and variables in a named block can be accessed by referring to its hierarchical name. The named blocks can also be terminated using the ‘disable’ keyword.
Named block example:
module tb;
reg [3:0] i1, i2, i3;
reg [3:0] x1, x2, x3;
// sequential block
initial begin: seq_blk1
$monitor("T = %0t: i1 = %0d, i2 = %0d, i3 = %0d, x1 = %0d, x2 = %0d, x3 = %0d", $time, i1, i2, i3, x1, x2, x3);
i1 = 3;
i2 = 2;
#4 i3 = 7;
end
initial begin: seq_blk2
#10;
// Parallel block
fork: par_blk1
x1 = i1;
#2 x2 = i2;
#5 x3 = i3;
join
#15 x1 = i1 + i2;
end
endmodule
Output:
T = 0: i1 = 3, i2 = 2, i3 = x, x1 = x, x2 = x, x3 = x
T = 4: i1 = 3, i2 = 2, i3 = 7, x1 = x, x2 = x, x3 = x
T = 10: i1 = 3, i2 = 2, i3 = 7, x1 = 3, x2 = x, x3 = x
T = 12: i1 = 3, i2 = 2, i3 = 7, x1 = 3, x2 = 2, x3 = x
T = 15: i1 = 3, i2 = 2, i3 = 7, x1 = 3, x2 = 2, x3 = 7
T = 30: i1 = 3, i2 = 2, i3 = 7, x1 = 5, x2 = 2, x3 = 7
Disable named block example:
module tb;
integer count = 0;
// Disable below count_loop block
initial begin
begin: count_loop
forever begin
count++;
$display("At T = %0t: count = %0d", $time, count);
if(count == 10) disable count_loop;
#5;
end
end
end
endmodule
Output:
At T = 0: count = 1
At T = 5: count = 2
At T = 10: count = 3
At T = 15: count = 4
At T = 20: count = 5
At T = 25: count = 6
At T = 30: count = 7
At T = 35: count = 8
At T = 40: count = 9
At T = 45: count = 10
Verilog Tutorials