Break and Continue in SystemVerilog

The break and continue keywords are used to control the loop flow. Both break and continue keywords can be used in all supported loops (while, do while, forever, for, foreach, repeat)

break keyword

The break keyword is used to terminate the loop prematurely. Generally, based on certain conditions the loop is terminated.

continue keyword

The continue keyword is used to jump the next iteration immediately without executing statements after the continue keyword.

break and continue Example

When a break keyword is used, the loop immediately is terminated by printing array elements having an index from 6 to 9.

When a continue keyword is used, the loop is skipped without printing the array element having an index 6.

module break_continue_example;
  int array[10];
  
  initial begin
    // Update array
    for (int i = 0; i < $size(array); i++) begin
      array[i] = i*i;
    end
  
    // Break keyword
    for (int i = 0; i < $size(array); i++) begin
      if(i == 6) break;
      $display("array[%0d] = %0d", i, array[i]);
    end
    $display("------------------------");
    
    // Contimue keyword
    for (int i = 0; i < $size(array); i++) begin
      if(i == 6) continue;
      $display("array[%0d] = %0d", i, array[i]);
    end
    $display("------------------------");
  end
endmodule

Output:

array[0] = 0
array[1] = 1
array[2] = 4
array[3] = 9
array[4] = 16
array[5] = 25
------------------------
array[0] = 0
array[1] = 1
array[2] = 4
array[3] = 9
array[4] = 16
array[5] = 25
array[7] = 49
array[8] = 64
array[9] = 81
------------------------

System Verilog Tutorials