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Data Types in System Verilog

A storage format having a specific range or type is called data type.

2 state data type: It has bits 0 and 1

4 state data type: It has bits 0, 1, X, and Z

Signed and Unsigned

Unsigned: can hold positive values alone.

Signed: can hold both positive and negative values.


Fixed value in the program is called literal. In simple terms, it is known as constants. Its value can not be altered during the execution of the program.


Variables can store any value in memory based on their data type. Its value can be changed during run time.


The value of constants cannot be changed. It is read-only in nature.

Integer data type


2 state data type, 32-bit signed integer


4 state data type, 32-bit signed integer


2 state data type, 16-bit signed integer


2 state data type, 64-bit signed integer


2 state data type, unsigned, user-defined vector size


2 state data type, 8-bit signed integer or ASCII character


4 state data type, unsigned, user-defined vector size


4 state data type, unsigned, user-defined vector size


4 state data type, 64-bit unsigned integer

Real, shortreal, and realtime data types

Real, shortreal, and realtime data types – Known as real variables.

real – same as double datatype in C

shortreal – same as a float in C

realtime – interchangeably used with the real data type.

void data type

Non-existence data is known as a void data type. It is usually used with functions where it’s return type is void.


An ordered collection of characters is called a string data type. The length of string variables may vary during simulation, hence the variable having type string is dynamic in nature.


Data type event is a handle to a synchronization object. The object which is referenced by an event variable can be triggered and waited for.

event is_empty; // declaration of is_empty event.

As proceeding further, we will discuss events in detail.

User-defined types

User-defined types use keyword typedef which is an extension of SystemVerilog data type.

typedef int myint;  // Declaration
myint a,b;          // Usage of user defined data type.


A set of integral named constants is called an enumerated type. It defines a set of named values having an anonymous int type.

enum {red, yellow, green} traffic_signal;
//Anonymous int type -> red = 0, yellow = 1 and green = 2

Logic data type

In Verilog behavior modeling, always, and initial procedural blocks use reg data type whereas, in dataflow modeling, continuous assignment uses wire data type. SystemVerilog allows driving signals in the ‘assign’ statements and procedural blocks using logic data type. The logic is a 4-state data type that allows capturing the Z or X behavior of the design.

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