Data Encapsulation and Hiding in SV

Data encapsulation is a mechanism that combines class properties and methods.

Data hiding is a mechanism to hide class members within the class. They are not accessible outside of class scope. This avoids class member modification outside the class scope and its misuse.

By default, all class members are accessible with class handles in SystemVerilog. To restrict access, access qualifiers are used.

Local Access Qualifier

If a class member is declared as a local, they will be available to that class alone. The child classes will not have access to a local class member of their parent class.

Local Access variable Examples

Access outside of the class scope

In the below example, the variable id is declared as a local variable. It is tried to access outside of class scope, which leads to a compilation error.

class transaction;
  bit [31:0] data;
  local int id;

  function void display();
    $display("data = %0d and id = %0d", data, id);
  endfunction
endclass

module class_example;
  transaction tr;
  
  initial begin
    tr = new();
   
    tr.data = 100;
    tr.id = 1;
    
    tr.display();
  end
endmodule

Output:

    tr.id = 1;
        |
       *E,CLSNLO (testbench.sv,17|8): Access to local member 'id' in class 'transaction' is not allowed here.

Access within the class scope

There is no compilation error expected if the local variable is accessed within the class scope.

class transaction;
  bit [31:0] data;
  local int id;

  function new();
    data = 100;
    id = 1;
  endfunction
  
  function void display();
    $display("data = %0d and id = %0d", data, id);
  endfunction
endclass

module class_example;
  transaction tr;
  
  initial begin
    tr = new();
    tr.display();
  end
endmodule

Output:

data = 100 and id = 1

Class methods as a local

Local Access method Examples

Access outside of the class scope

A class method display() is declared as local. So, calling the display() method outside of the class scope will lead to a compilation error.

class transaction;
  bit [31:0] data;
  int id;

  function new();
    data = 100;
    id = 1;
  endfunction
  
  local function void display();
    $display("data = %0d and id = %0d", data, id);
  endfunction
endclass

module class_example;
  transaction tr;
  
  initial begin
    tr = new();
    tr.display();
  end
endmodule

Output:

 tr.display();
     |
 *E,CLSNLO (testbench.sv,20|13): Access to local member 'display' in class 'transaction' is not allowed here.

Access within the class scope

There is no compilation error expected if the local display() method is accessed within the class scope.

class transaction;
  bit [31:0] data;
  int id;

  function new();
    data = 100;
    id = 1;
    display();
  endfunction
  
  local function void display();
    $display("data = %0d and id = %0d", data, id);
  endfunction
endclass

module class_example;
  transaction tr;
  
  initial begin
    tr = new();
  end
endmodule

Output:

data = 100 and id = 1

The child class access local member of the parent class

A child_trans is a derived class of base class transaction. A local method display() is defined in the base class and it is accessed by its child class child_trans. Since it is not allowed, a compilation error is expected.

class transaction;
  bit [31:0] data;
  int id;

  function new();
    data = 100;
    id = 1;
  endfunction
  
  local function void display();
    $display("data = %0d and id = %0d", data, id);
  endfunction
endclass

class child_trans extends transaction;
  bit [31:0] addr;
  
  task calc_addr;
    addr = data * id;
    display();  // child class is accessing local method of parent class
    $display("addr = %0d", addr);
  endtask
endclass

module class_example;
  child_trans tr;
  
  initial begin
    tr = new();
    tr.calc_addr();
  end
endmodule

Output:

 display();  // child class is accessing local method of parent class
          |
     *E,CLSNLO (testbench.sv,22|10): Access to local member 'display' in class 'transaction' is not allowed here.

System Verilog Tutorials