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In certain cases, the class handle of another class is required even if it is not declared yet. In such cases, SystemVerilog provides a forward declaration of the class using the typedef keyword.

Syntax:

typedef class <class_name>

Without typedef keyword

In the example, the tr_B class object is created inside the transaction_A class even though the transaction_B class definition is unknown. So, the compilation error is expected.

class transaction_A;
  bit [31:0] data;
  int id;
  transaction_B tr_B = new();
      
  function void display();
    $display("transaction_A: data = %0d and id = %0d", data, id);
    $display("transaction_B: addr = %0d", tr_B.addr);
  endfunction
endclass

class transaction_B;
  bit [31:0] addr = 200;
endclass

module class_example;
  transaction_A tr_A;
  
  initial begin
    tr_A = new();
   
    tr_A.data = 100;
    tr_A.id = 1;
    tr_A.display();
  end
endmodule

Output:

  transaction_B tr_B = new();
              |
       *E,NOIPRT (testbench.sv,6|14): Unrecognized declaration 'transaction_B' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
  transaction_B tr_B = new();

With typedef keyword

The forward declaration is done with a typedef declaration as follows.

typedef class transaction_B;

class transaction_A;
  bit [31:0] data;
  int id;
  transaction_B tr_B = new();
      
  function void display();
    $display("transaction_A: data = %0d and id = %0d", data, id);
    $display("transaction_B: addr = %0d", tr_B.addr);
  endfunction
endclass

class transaction_B;
  bit [31:0] addr = 200;
endclass

module class_example;
  transaction_A tr_A;
  
  initial begin
    tr_A = new();
   
    tr_A.data = 100;
    tr_A.id = 1;
    tr_A.display();
  end
endmodule

Output:

transaction_A: data = 100 and id = 1
transaction_B: addr = 200

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