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As the name suggests, a forever loop runs indefinitely. To terminate the loop, a break statement can be used.

Syntax:

forever begin
...
end

forever loop Examples

Example with $finish

To terminate the loop, $finish system call is used.

module forever_example;  
  int count;
  initial begin
    forever begin 
      $display("Value of count = %0d", count);
      count++;
      #5;
    end
  end
  
  initial begin
    #30;
    $finish;
  end
endmodule

Output:

Value of count = 0
Value of count = 1
Value of count = 2
Value of count = 3
Value of count = 4
Value of count = 5
$finish called from file "testbench.sv", line 16.
$finish at simulation time 30

Example with a break statement

The break statement is used in the below example to terminate the loop based on the condition. The break statement will be discussed under the break and continue section.

module forever_example;  
  int count;
  initial begin
    forever begin 
      $display("Value of count = %0d", count);
      count++;
      if(count == 10) break;
    end
  end
endmodule

Output:

Value of count = 0
Value of count = 1
Value of count = 2
Value of count = 3
Value of count = 4
Value of count = 5
Value of count = 6
Value of count = 7
Value of count = 8
Value of count = 9

Difference between always and forever block

Both always and forever block the same effect. The always block is a procedural block and it can not be placed inside other procedural blocks. Also, always block can not be used inside the class.

Syntax for always block:

// For multiple statements in always block
always begin
...
end

// For single statement
always <single statement>

Example of always block

module always_example;  
  int count;
  always begin
    $display("Value of count = %0d", count);
    count++;
    #5;
  end
  
  initial begin
    #30;
    $finish;
  end
endmodule

Output:

Value of count = 0
Value of count = 1
Value of count = 2
Value of count = 3
Value of count = 4
Value of count = 5
$finish called from file "testbench.sv", line 14.
$finish at simulation time 30

A always block inside another procedural block

A compilation error is expected when always block is used inside another procedural block. In such a case, a forever block can be used.

module always_example;  
  int count;
  initial begin
    always begin // can not use inside other procedural block
      $display("Value of count = %0d", count);
      count++;
      #5;
    end
  end
  
  initial begin
    #30;
    $finish;
  end
endmodule

Output:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "testbench.sv", 7: token is 'always'
      always begin // can not use inside other procedural block
            ^
1 error

A always block inside a class

A compilation error is expected when always block is used inside a class. We will discuss the concept of class in the upcoming section.

class transaction;
  int count;
  
  task inc_cnt();
    always begin
      $display("Value of count = %0d", count);
      count++;
      #5;
    end
  endtask
endclass

module always_example;
  transaction tr;
  initial begin
    tr = new();
    tr.inc_cnt();
  end
  
  initial begin
    #100;
    $finish;
  end
endmodule

Output:

    always begin
         |
xmvlog: *E,ALWILL (testbench.sv,8|9): The always construct is illegal in this context.

forever loop inside a class

Now, replace always block with forever block.

class transaction;
  int count;
  
  task inc_cnt();
    forever begin
      $display("Value of count = %0d", count);
      count++;
      #5;
    end
  endtask
endclass

module always_example;
  transaction tr;
  initial begin
    tr = new();
    tr.inc_cnt();
  end
  
  initial begin
    #100;
    $finish;
  end
endmodule

Output:

Value of count = 0
Value of count = 1
Value of count = 2
Value of count = 3
Value of count = 4
Value of count = 5
Value of count = 6
Value of count = 7
Value of count = 8
Value of count = 9
Value of count = 10
Value of count = 11
Value of count = 12
Value of count = 13
Value of count = 14
Value of count = 15
Value of count = 16
Value of count = 17
Value of count = 18
Value of count = 19
Simulation complete via $finish(1) at time 100 NS + 0
./testbench.sv:25     $finish;

System Verilog Tutorials