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if statement in SystemVerilog

if statement

SystemVerilog supports ‘if’, ‘else if’, ‘else’ same as other programming languages. 

The ‘If’ statement is a conditional statement based on which decision is made whether to execute lines inside ‘if’ block or not.

The begin and end are required in case of multiple lines present in ‘if’ block. For single-line inside ‘if’ statement may not require ‘begin..end’

The ‘if’ statement returns true if the expression calculates its value as 1 otherwise, for 0, x, z values ‘if’ block will not be executed.

Syntax:

if(<condition>) begin
  ...
end

The else if or else statement

In case, ‘if’ statement does not hold true, ‘else if’ or ‘else’ will be executed. For any condition hold true in ‘else if’ statement, subsequent ‘else if’ or ‘else’ statement will not be checked.

Syntax: ‘else if’ and ‘else’ condition


if(<condition>) begin
  ...
end
else if(<condition>) begin
  ...
end 
else if(<condition>) begin
  ...
end
else begin
  ...
end


Syntax: if and else condition
if(<condition>) begin
  ...
end
else begin
  ...
end

If statement Example

module if_example;  
  initial begin
    int a, b;
    a = 10;
    b = 20;
    if(a>b)
      $display("a is greater than b");
    else if(a<b)
      $display("a is less than b");
    else 
      $display("a is equal to b");
  end
endmodule

Output:

a is less than b

SystemVerilog unique if

SystemVerilog allows us to use a ‘unique’ keyword before ‘if’ statement. Following error/warnings are expected:

  1. None of ‘if’ conditions are true or there is no ‘else’ statement.
  2. More than one ‘if’ or ‘else if’ conditions are true.

unique if Example

module unique_if_example;  
  initial begin
    int a, b;
    a = 10;
    b = 20;
    unique if(a>b)
      $display("a is greater than b");
    else if(a<b)
      $display("a is less than b");
    else 
      $display("a is equal to b");
  end
endmodule

Output:

a is less than b

An error/ warning Example

None of if conditions are true or there is no ‘else’ statement

In the below example, no ‘if’ or ‘else if’ the condition is true. Also, ‘else’ condition is not written. Hence, run time error/ warning is expected.

module unique_if_example;  
  initial begin
    int a, b;
    a = 10;
    b = 20;
    unique if(a>30)
      $display("a is greater than 30");
    else if(30<b)
      $display("30 is less than b");
  end
endmodule

Output:

Warning-[RT-NCMUIF] No condition matches in statement
testbench.sv, 9
  No condition matches in 'unique if' statement. 'else' statement is missing 
  for the last 'else if' block, inside unique_if_example.unnamed$$_0, at time 
  0ns.

More than one if or else if conditions are true

In the below example, more that ‘if’ or ‘else if’ condition is true which issues a compilation error/ warning.

module unique_if_example;  
  initial begin
    int a, b;
    a = 10;
    b = 20;
    unique if(a>b)
      $display("a is greater than b");
    else if(a<b)
      $display("a is less than b");
    else if(a<50)
      $display("a is less than 50");
    else 
      $display("a is equal to b");
  end
endmodule

Output:

a is less than b

Warning-[RT-MTOCMUIF] More than one condition match in statement
testbench.sv, 9
  More than one condition matches are found in 'unique if' statement inside 
  unique_if_example.unnamed$$_0, at time 0ns.
  
  Line number 11 and 13 are overlapping.

SystemVerilog unique0 if

The unique0 if/ else if statement does not issue any run time warning unlike the unique if statement.

None of if conditions are true or there is no ‘else’ statement

No run time warning is expected even if there is no ‘if’/ ‘else if’ a condition is true or else the condition is missing.

module unique0_if_example;  
  initial begin
    int a, b;
    a = 10;
    b = 20;
    unique0 if(a>30)
      $display("a is greater than 30");
    else if(30<b)
      $display("30 is less than b");
  end
endmodule

Output:

// No run time warning is observed.

SystemVerilog priority if

The execution of ‘priority if’ is in sequential order.

priority if Example

module priority_if_example;  
  initial begin
    int a, b;
    a = 20;
    b = 10;
    priority if(a>b)
      $display("a is greater than b");
    else if(a<b)
      $display("a is less than b");
    else 
      $display("a is equal to b");
  end
endmodule

Output:

a is greater than b

The simulation issues following run time error/warning

None of ‘if’ conditions are true or there is no ‘else’ statement.

An error/ warning example

None of if conditions are true or there is no ‘else’ statement

In the below example, no ‘if’ or ‘else if’ a condition is true. Also, ‘else’ condition is not written. Hence, run time error/ warning is expected.

module priority_if_example;  
  initial begin
    int a, b;
    a = 20;
    b = 10;
    priority if(a>30)
      $display("a is greater than 30");
    else if(30<b)
      $display("30 is less than b");
  end
endmodule

Output:

Warning-[RT-NCMPRIF] No condition matches in statement
testbench.sv, 9
  No condition matches in 'priority if' statement. 'else' statement is missing
  for the last 'else if' block, inside priority_if_example.unnamed$$_0, at 
  time 0ns.

System Verilog Tutorials