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Implication operator (->) declares the relation between two variables. For an implication operator in constraint, it declares the relation between expression and constraint.

If the LHS expression of -> holds true, the RHS constraint is considered.

Syntax:

<expression> -> <constraint>

Implication operator in constraint example

class seq_item;
  rand bit [7:0] value;
  rand enum {LOW, HIGH} scale;

  constraint scale_c { (scale == LOW) -> value <50; }
endclass

module constraint_example;
  seq_item item;
  
  initial begin
    item = new();
    
    repeat(5) begin
      item.randomize();
      $display("scale = %s, value = %0d", item.scale.name(), item.value);
    end
  end
endmodule

Output:

scale = HIGH, value = 150
scale = HIGH, value = 121
scale = HIGH, value = 192
scale = HIGH, value = 104
scale = LOW, value = 33

System Verilog Tutorials