Repeat loop in SystemVerilog

A repeat loop is used to execute statements a given number of times.

Syntax:

repeat(<number>) begin   // <number> can be variable or fixed value
  ...
end

repeat loop Example

In the below example,

Based on the array size, array elements are printed.
The string “Repeat it” is printed three times.

module repeat_example;
  int array[5] = '{100, 200, 300, 400, 500};
  int i;
  initial begin
    repeat ($size(array)) begin
      $display("array[%0d] = %0d", i, array[i]);
      i++;
    end
    
    repeat(3)
      $display("VLSI Verify");
  end
endmodule

Output:

array[0] = 100
array[1] = 200
array[2] = 300
array[3] = 400
array[4] = 500
VLSI Verify
VLSI Verify
VLSI Verify

System Verilog Tutorials