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The initial block occurs at the start of simulation whereas the final block occurs at end of the simulation without having any delays. So, it is the same as a function call that can execute in zero simulation time.

The main usage of the final block is to display statistical information about the simulation

Syntax:

final begin
  ...
end

final block example

module final_example;
  initial begin
    $display("Inside initial block");
    #10;
    $display("Before calling $finish");
    $finish;
  end
  
  final begin
    $display("Inside final block at %0t", $time);
  end
endmodule

Output:

Inside initial block
Before calling $finish
$finish called from file "testbench.sv", line 8.
Inside final block at 10
$finish at simulation time 10

System Verilog Tutorials