AHB Introduction

AHB is part of the AMBA family of on-chip bus protocols. It is designed for higher-performance data movement than APB while remaining simpler than multi-channel protocols such as AXI. AHB is useful when a design needs pipelined transfers, burst support, and a clean synchronous interface.

At a system level, AHB defines how an active bus component starts a transfer, how address/control information is presented, how write or read data moves, and how the selected target reports completion or error. It is not a memory controller by itself and it is not a complete interconnect implementation by itself. Instead, it is the interface contract that lets Managers, Subordinates, bridges, and interconnect blocks communicate predictably.

AHB is especially useful in designs where a simple register bus would become a bottleneck. It supports one transfer address phase overlapping another transfer data phase, so a well-designed zero-wait-state system can complete one transfer per cycle after the pipeline is filled. This makes it suitable for traffic that is more demanding than APB peripheral access but does not need the full complexity of AXI.

The protocol is usually used for:

Processor instruction and data paths.
Internal SRAM or tightly coupled memory access.
DMA traffic.
External memory controllers.
Higher-bandwidth peripheral interfaces.
Bridges to APB, AXI, or other bus fabrics.

AHB is commonly seen in microcontroller-class and embedded SoC designs because it balances performance and implementation cost. A small system might use one Manager, a decoder, and a few Subordinates. A larger system might use a multi-layer interconnect so multiple Managers can access different Subordinates in parallel.

The most important idea is that AHB separates a transfer into an address phase and a data phase. These phases are pipelined, so the address phase of one transfer can overlap with the data phase of the previous transfer. This overlap gives AHB better throughput than a non-pipelined register bus.

For beginners, the useful mental model is:

The Manager announces what it wants during the address phase.
The selected Subordinate completes the transfer during the data phase.
HREADY controls whether the pipeline can advance.
HRESP reports whether the transfer completed successfully or with an error.
Burst, protection, security, user, and parity signals add context around the same basic transfer flow.

AHB system roles

To stay aligned with current engineering standards and the latest official Arm AMBA specifications, this guide uses modernized terminology. Legacy codebases, older documentation, and classic textbooks may use Master/Slave conventions, but contemporary AMBA specifications define the roles as Manager, Subordinate, and Interconnect.

The underlying clock-edge mechanics and protocol concepts remain exactly the same. Only the terminology has been updated so the tutorial matches today’s Arm AMBA ecosystem.

Role	Typical implementation	Main job
Manager	Formerly Master; CPU bus interface, DMA engine, bridge, debug port	Active component that initiates read or write operations and drives address, control, and write data
Subordinate	Formerly Slave; SRAM, peripheral, bridge, memory controller	Passive component that responds to selected requests from a Manager and returns read data, ready, and response
Interconnect	Decoder, mux, arbiter, routing fabric	Routing and arbitration logic that manages traffic between Managers and Subordinates

In a single-Manager AHB system, the interconnect can be simple. A decoder watches HADDR and asserts one HSELx select line. A response multiplexor returns HRDATA, HREADYOUT, and HRESP from the selected Subordinate back to the Manager.

In a multi-Manager system, the interconnect also performs arbitration and routing. The AHB protocol defines the interface behavior, but a complete multi-layer interconnect can add internal policy around priority, arbitration, and route timing.

AHB compared with APB

Feature	AHB	APB
Main purpose	Higher-bandwidth system traffic	Low-bandwidth register access
Transfer style	Pipelined address and data phases	Setup and Access phases
Burst support	Yes	No
Wait-state support	HREADY and HREADYOUT	PREADY
Error response	HRESP	PSLVERR
Typical targets	Memory, DMA, bridges, high-speed peripherals	Timers, GPIO, UART registers, control blocks

APB is often connected behind an AHB-to-APB bridge. The bridge appears as an AHB Subordinate on the AHB side and as an APB Requester on the APB side.

AHB Protocol