Exclusive Transfers

AHB5 can support Exclusive Transfers using the Exclusive_Transfers property. Exclusive Transfers support semaphore-style software sequences.

The common sequence is:

Manager performs an Exclusive Read using HEXCL.
Exclusive Access Monitor records the address and Manager identity.
Manager computes a new value.
Manager performs an Exclusive Write to the same address.
Monitor returns success or failure using HEXOKAY.

If another Manager writes the monitored location between the Exclusive Read and Exclusive Write, the Exclusive Write fails and must not update memory. Software usually retries the sequence. Non-exclusive transfers can occur between the Exclusive Read and Exclusive Write.

The monitor must be able to track at least one address for each Exclusive-capable Manager. Its location is implementation defined, but it must observe all address locations that support Exclusive access. Systems can support Exclusive sequences for main memory but fail them for unsupported regions such as many peripheral registers.

Exclusive signals

Signal	Phase	Purpose
HEXCL	Address phase	Marks an Exclusive Transfer.
HMASTER	Address phase	Identifies the Manager or thread for monitor tracking. It must be valid for all transfers, not only exclusive transfers.
HEXOKAY	Data phase response	Reports success or failure of an Exclusive Transfer.

Recommended HMASTER widths depend on interface role: Managers implement enough bits for their exclusive-capable threads, interconnect ports often use 4 bits, and Subordinates or monitors often use 8 bits.

HEXOKAY has strict response rules:

Rule	Meaning
Assert only with HREADY HIGH	Exclusive status is valid only when the transfer completes.
Assert only for Exclusive Transfers	Non-exclusive transfers must not receive asserted HEXOKAY.
Do not assert with HRESP=ERROR	ERROR and Exclusive OKAY success cannot be reported together.
Deasserted on failed Exclusive Write	Memory must not be updated on failure.

Exclusive restrictions

Restriction	Reason
Exclusive Transfer must be single beat	Monitor checks one access at a time.
Burst type must be SINGLE or INCR	No fixed-length multi-beat exclusive bursts.
No BUSY transfer	The exclusive access is a single real transfer.
Address aligned to HSIZE	Required for matching and atomic behavior.
HPROT must allow monitor visibility	Cache/buffer placement can hide accesses from the monitor.
Matching Exclusive Read and Exclusive Write fields must match	HADDR, HSIZE, HPROT, HBURST, HMASTER, and HNONSEC if present.
Exclusive Write without matching Exclusive Read must fail	HEXOKAY must be deasserted.
A Manager must not have two Exclusive Transfers outstanding	Do not issue a new Exclusive address phase while the previous Exclusive data phase is active for the same HMASTER.

Exclusive transfer checklist

Check	Reason
Exclusive monitor tracks address and Manager identity	Needed to validate the matching write.
Failed Exclusive Write does not update memory	Required for correct software retry behavior.
HEXOKAY is routed through the interconnect	Manager must see success or failure.
Illegal exclusive combinations are tested	Edge cases often expose monitor bugs.

AHB Protocol