Basic Transfers

The AHB specification introduces pipelining as part of the basic transfer model.

Every AHB transfer has two phases:

Phase	Meaning
Address phase	Manager drives address and control information.
Data phase	Write data is accepted or read data is returned, and the transfer response is completed.

The address phase normally lasts one clock cycle. The data phase lasts one or more clock cycles. A Subordinate cannot directly extend the address phase of the current transfer, but by extending the previous data phase it also prevents the next address phase from advancing.

In the shortest case, one transfer completes every cycle after the pipeline is filled. This is the key performance idea:

Cycle T0: address phase for transfer A.
Cycle T1: data phase for transfer A and address phase for transfer B.
Cycle T2: data phase for transfer B and address phase for transfer C.

Why AHB is pipelined

Pipelining gives the Subordinate one full cycle to decode an address and prepare a response. At the same time, the Manager can already place the next address on the bus. This improves throughput without requiring multiple independent read/write channels.

The cost is that error and wait behavior must account for a following transfer that might already be visible on the bus. That is why AHB has careful rules for HREADY, HRESP, and address/control stability.

The mental model

Keep these rules in mind:

Address/control information belongs to the address phase.
HWDATA belongs to the data phase of a write.
HRDATA, HREADY, and HRESP belong to the data phase response.
When HREADY is LOW, the current data phase is still active.
When a data phase is stalled, the next address phase is also held.

This phase split is the source of many beginner bugs. If a Subordinate samples write data in the address phase, or if a Manager changes control signals while HREADY is LOW, the design is likely wrong.

Transfer direction

AHB uses HWRITE to select transfer direction:

HWRITE	Direction	Data bus used
0	Read	HRDATA from Subordinate to Manager
1	Write	HWDATA from Manager to Subordinate

Read transfer

The waveform below shows a read transfer with two wait states. It is useful because it shows both the basic read behavior and the way AHB pipelining lets the next address appear while the current read data phase is still completing.

The Manager drives HADDR, HTRANS, HWRITE=0, HSIZE, and other control signals.
The selected Subordinate samples the address/control information when HREADY is HIGH.
The data phase starts in the next cycle, but the Subordinate can hold HREADY LOW to insert wait states.
During the wait states, HRDATA does not have to contain valid read data.
The Subordinate drives valid HRDATA in the final data-phase cycle.
The transfer completes when HREADY is HIGH and HRESP is OKAY.

In this example, address A is the read transfer being completed, while address B is already visible as the next address phase. The important rule is that read data for address A is only required to be valid when the transfer completes.

Write transfer

The waveform below shows a write transfer with one wait state. It highlights the most important write rule: once the write data phase begins, the Manager must keep HWDATA stable until the transfer completes.

The Manager drives address and control in the address phase.
In the following data phase, the Manager drives HWDATA.
The selected Subordinate can hold HREADY LOW to insert a wait state.
While HREADY is LOW, the Manager must keep HWDATA stable.
The selected Subordinate samples HWDATA when the transfer completes.
The transfer completes when HREADY is HIGH and HRESP is OKAY.

In this example, address A is the write transfer being completed, while address B is already visible as the next address phase. The write data for address A remains valid through the wait state and is accepted only when HREADY returns HIGH.

Basic transfer checklist

Check	Why it matters
HTRANS is NONSEQ for a single real transfer	Subordinate must know the transfer is valid.
HWRITE is stable while stalled	Direction cannot change mid-transfer.
Write data is driven in the data phase	AHB write data is not address-phase data.
Read data is sampled only on completion	Read data can be invalid during wait states.
Response is sampled with ready	HRESP is meaningful as part of the data-phase response.

AHB Protocol