Waited Transfers
Subordinates use HREADYOUT to insert wait states when they need more time to provide read data, sample write data, or complete an internal operation. The interconnect selects the active Subordinate’s HREADYOUT and returns it as HREADY.
When HREADY is LOW, the current data phase is not complete. This also holds the next address phase, so the Manager is restricted in what it can change on HTRANS and HADDR.
| Signal | Role during a waited transfer |
|---|---|
| HREADYOUT | Driven by the selected Subordinate to request wait states or complete the transfer. |
| HREADY | Returned to the Manager and Subordinates to indicate whether the current data phase has completed. |
| HTRANS | Normally held stable while waited, except for the specific IDLE/BUSY cases below. |
| HADDR | Normally held stable while waited, except during waited IDLE and after ERROR response cases. |
The basic wait-state read, wait-state write, and address-phase extension examples are already covered in Basic Transfers using Figure 3-3, Figure 3-4, and Figure 3-5. This section focuses on the waited-transfer rules from the specification.
Transfer type changes during wait states
When the Subordinate is requesting wait states, the Manager must not change HTRANS freely. The specification permits only the following cases.
| Waited condition | Allowed change | Effect |
|---|---|---|
| IDLE transfer | IDLE to NONSEQ | The Manager can prepare a real transfer while the previous data phase is waited. Once NONSEQ is driven, it must remain constant until HREADY is HIGH. |
| BUSY in a fixed-length burst | BUSY to SEQ | Applies to INCR4, INCR8, INCR16, WRAP4, WRAP8, and WRAP16. Once SEQ is driven, it must remain constant until HREADY is HIGH. |
| BUSY in undefined-length INCR burst | BUSY to SEQ, IDLE, or NONSEQ | SEQ continues the burst. IDLE or NONSEQ terminates the undefined-length burst. |
| Other active transfer | No normal change | Address/control must remain stable until the transfer progresses. q |
IDLE to NONSEQ
It shows a waited SINGLE transfer followed by a new INCR4 transfer. The important rule is that IDLE can change to NONSEQ during a wait, but after NONSEQ appears it must be held until HREADY is HIGH.
| Time | What the waveform shows |
|---|---|
| T0-T1 | The Manager starts a SINGLE transfer to address A. |
| T1-T2 | The Manager drives an IDLE transfer to address Y, while the Subordinate inserts a wait state. |
| T2-T3 | The Manager continues with another IDLE transfer, now showing address Z. |
| T3-T4 | The Manager changes from IDLE to NONSEQ and prepares an INCR4 burst starting at address B. |
| T4-T6 | Because HREADY is LOW, the Manager must hold HTRANS=NONSEQ stable. |
| T5-T6 | The earlier SINGLE transfer to address A completes, and the prepared transfer to B becomes active. |
| T6-T7 | The first beat at B completes and the next sequential beat starts at B+4. |
BUSY to SEQ for a fixed-length burst
It shows a fixed-length INCR4 burst where the Manager inserts BUSY before the next real beat. For fixed-length bursts, BUSY can change to SEQ during a wait, but the burst must continue with real SEQ transfers.
| Time | What the waveform shows |
|---|---|
| T0-T1 | The Manager issues the next INCR4 burst beat at address 0x24. |
| T1-T3 | The Manager drives BUSY for the next intended address 0x28, while the Subordinate inserts wait states. |
| T3-T4 | The Manager changes HTRANS from BUSY to SEQ and issues the real transfer at address 0x28. |
| T4-T6 | HREADY is LOW, so the Manager must hold HTRANS=SEQ stable. |
| T5-T6 | The beat at address 0x24 completes. |
| T6-T7 | The beat at address 0x28 completes, and the final beat of the INCR4 burst starts at 0x2C. |
BUSY to NONSEQ for an undefined length burst
It shows an undefined-length INCR burst ending during a waited BUSY transfer. Unlike fixed-length bursts, an undefined-length burst can terminate when the Manager changes from BUSY to IDLE or NONSEQ.
| Change | Result |
|---|---|
| SEQ | Continue the current undefined-length burst. |
| IDLE | Terminate the current undefined-length burst. |
| NONSEQ | Terminate the current burst and start a new unrelated transfer or burst. |
| Time | What the waveform shows |
|---|---|
| T0-T1 | The Manager issues the next beat of an undefined-length INCR burst at address 0x64. |
| T1-T3 | The Manager drives BUSY for the next intended address 0x68, while the Subordinate inserts wait states. |
| T3-T4 | The Manager changes from BUSY to NONSEQ, terminating the undefined-length burst and starting a new burst at address 0x10. |
| T4-T6 | HREADY is LOW, so the new NONSEQ transfer must remain stable. |
| T5-T6 | The previous undefined-length burst completes. The first beat of the new burst at 0x10 becomes active. |
| T6-T7 | The first beat at 0x10 completes and the next beat starts at 0x14. |
Address changes during wait states
The address is also controlled during waited transfers. In general, the Manager can only change the address once while HREADY is LOW, except for the specific cases shown below.
| Situation | Address rule |
|---|---|
| Waited IDLE transfers | The Manager can change address while HTRANS remains IDLE. Once HTRANS changes to NONSEQ, the address must remain constant until HREADY is HIGH. |
| Waited BUSY to SEQ | The address represents the next intended burst beat and must remain stable once SEQ is driven. |
| After an ERROR response | The Manager is permitted to change address while HREADY is LOW to cancel or redirect the following pipelined transfer. |
| Normal waited transfer | Address/control remain stable. |
Address changes during a waited transfer, with an IDLE transfer
It focuses on address behavior while the Manager is driving waited IDLE transfers. Address can change while HTRANS remains IDLE, but once the Manager changes to NONSEQ, the new address must remain stable until HREADY is HIGH.
| Time | What the waveform shows |
|---|---|
| T0-T1 | The Manager starts a SINGLE transfer to address A. |
| T1-T2 | The Manager drives an IDLE transfer and shows address Y; the Subordinate inserts a wait state. |
| T2-T3 | The Manager continues with IDLE and changes the address to Z. |
| T3-T4 | The Manager changes to NONSEQ and starts an INCR4 burst at address B. |
| T4-T6 | No more address changes are allowed while HREADY remains LOW. Address B must be held. |
| T5-T6 | The earlier SINGLE transfer to address A completes and the first beat at B becomes active. |
| T6-T7 | The first beat at B completes and the next beat starts at B+4. |
This rule prevents a Subordinate or monitor from treating an address seen during a waited IDLE cycle as a completed real transfer.
Address changes during a waited transfer, after an ERROR
It shows the special address-change exception that applies after an ERROR response. Because AHB is pipelined, the following transfer address can already be visible when ERROR is reported. The Manager is allowed to change address and drive HTRANS=IDLE while HREADY is LOW to cancel that following transfer.
| Time | What the waveform shows |
|---|---|
| T0-T1 | The Manager issues a burst beat at address 0x24. |
| T1-T3 | The Manager issues the next beat at address 0x28, and the Subordinate still indicates OKAY. |
| T3-T4 | The Subordinate starts an ERROR response. |
| T4-T5 | The Manager drives HTRANS=IDLE and changes the address to 0xC0 while HREADY is LOW; this cancels the following pipelined transfer. |
| T5-T6 | The ERROR response has completed, and the Subordinate selected by address 0xC0 responds OKAY. |
The important point is that this is an ERROR-specific exception. Normal waited transfers still require address/control stability.
Waited transfer checklist
| Check | Reason |
|---|---|
| Gate address/control sampling with HREADY | Prevents accepting a transfer before the previous data phase completes. |
| Hold real NONSEQ or SEQ transfer type while waited | Prevents the next real transfer from changing mid-wait. |
| Allow IDLE to NONSEQ only with stability after NONSEQ | Matches the spec’s waited IDLE rule. |
| Allow fixed-burst BUSY to SEQ, not arbitrary types | Fixed-length bursts must continue legally. |
| Allow undefined INCR BUSY to terminate with IDLE or NONSEQ | Undefined-length bursts can end after a waited BUSY. |
| Treat ERROR as a special address-change exception | Allows cancellation of the following pipelined transfer. |
AHB Protocol