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Interface Protection Using Parity
The AHB parity feature adds check signals that protect groups of AHB interface signals. It is intended for systems that need detection of transient or functional wire errors across component boundaries.
The Check_Type property controls whether check signals exist:
| Check_Type | Meaning |
|---|---|
| False | No check signals. If the property is not declared, it is treated as False. |
| Odd_Parity_Byte_All | Odd parity checking is included for all defined signal groups. |
Odd parity means the protected payload bits plus the check bit are driven so the group contains an odd number of asserted bits.
Parity signal rules
| Rule | Meaning |
|---|---|
| Most parity bits cover up to 8 payload bits | Keeps generation logic small enough for timing. |
| Critical control signals can use one check bit | For a single protected control bit, odd parity is the inversion of that bit. |
| Wider check signals map by byte groups | Check bit n covers payload bits [(8n+7):8n]; the most significant group can cover fewer than 8 bits. |
| Check signals are driven when their Check Enable term is true | Validity depends on the protected signal group. |
| Data parity covers all payload bits | Even inactive byte lanes still need correct HWDATACHK/HRDATACHK generation. |
| Missing protected signals are treated as LOW | If some covered optional signals are absent, parity assumes zero for those bits. |
| Omit unused check signals | If none of the covered signals exist on an interface, the corresponding check signal is absent. |
Examples of check signal groups include:
| Check signal | Protects | Check enable idea |
|---|---|---|
| HTRANSCHK | HTRANS | HRESETn |
| HADDRCHK | HADDR | HRESETn |
| HCTRLCHK1 | HBURST, HMASTLOCK, HWRITE, HSIZE, HNONSEC | HTRANS != IDLE |
| HCTRLCHK2 | HEXCL, HMASTER | HTRANS != IDLE |
| HPROTCHK | HPROT | HTRANS != IDLE |
| HWSTRBCHK | HWSTRB | Write data phase |
| HWDATACHK | HWDATA | Write data phase |
| HRDATACHK | HRDATA | Read data phase and HREADY |
| HREADYCHK, HREADYOUTCHK | Ready signaling | HRESETn |
| HRESPCHK | HRESP, HEXOKAY | Data phase |
| HSELxCHK | HSELx | HRESETn |
| User check signals | HAUSER, HWUSER, HRUSER, HBUSER | Matching User signal phase |
Error detection behavior
The AHB parity scheme defines the signals, not a single mandatory recovery action. When parity mismatch is detected, the receiver can terminate or propagate the transaction, correct or propagate the parity error, update memory or leave it untouched, or signal error through another system mechanism such as an interrupt. The transaction response is independent of parity detection unless the system explicitly connects the two.
Parity protection checklist
| Check | Reason |
|---|---|
| Check signals are generated from the correct cycle | Parity must match protected data. |
| Check enable conditions match the protected phase | Prevents false parity failures on invalid cycles. |
| Data parity includes inactive byte lanes | The parity rule covers the payload bits, not only active strobes. |
| Parity error behavior is documented | Software and safety monitors need a policy. |
| Parity configurations are included in compatibility tests | Configurable IP fails easily at optional-feature boundaries. |
AHB Protocol