Clock-Reset and Signal Validity

AHB is synchronous. Protocol signals are sampled on the rising edge of HCLK, and output signal changes occur after the rising edge.

Clock

All bus timing is relative to HCLK. Managers, Subordinates, and interconnect logic must agree on the sampling edge. Clock-domain crossing is not part of the basic AHB signal-level protocol; if a bridge crosses clock domains, it must preserve AHB behavior at each interface.

When the specification says a signal is stable, it means the value sampled on rising clock edges must remain the same across an extended transfer. It does not always require the signal to be glitch-free between clock edges. AHB5 defines the Stable_Between_Clock property for interfaces that guarantee required-stable signals remain glitch-free between rising edges.

Reset

HRESETn is active LOW and is the only active-LOW signal in the protocol. It can be asserted asynchronously, but it is deasserted synchronously after a rising edge of HCLK.

Each component must define the minimum number of reset cycles needed for a full reset. During reset:

Component	Reset requirement
Manager	Address/control outputs must be valid, and HTRANS[1:0] must indicate IDLE.
Subordinate	HREADYOUT must be HIGH.

Signal Validity

When signals are not required to be valid, they can take any value, but the specification recommends 0 or X. For invalid byte lanes in a data transfer, driving 0 is recommended to avoid leaking data between transactions.

Validity rule	Signals
Always valid	HTRANS, HADDR, HSEL, HMASTLOCK, HREADY, HREADYOUT, HRESP
Valid when HTRANS is not IDLE	HBURST, HPROT, HSIZE, HNONSEC, HEXCL, HMASTER, HWRITE, HAUSER
Valid during write data phase	HWDATA, HWSTRB, HWUSER
Valid in write data phase when HREADY HIGH and HRESP LOW	HEXOKAY, HBUSER
Valid in read data phase when HREADY HIGH and HRESP LOW	HRDATA, HEXOKAY, HRUSER, HBUSER

Stability during waits

When HREADY is LOW, the transfer is extended. Address/control and data-phase signals must remain stable according to their phase, except for the explicit waited-transfer exceptions described earlier.

Example assertion idea:

property ahb_addr_ctrl_stable_when_waiting;
  @(posedge HCLK) disable iff (!HRESETn)
    !HREADY |=> $stable({HADDR, HWRITE, HSIZE, HBURST, HTRANS, HPROT});
endproperty

The exact set of signals depends on implemented optional features. If HNONSEC, HEXCL, HMASTER, or user signals exist, include them in the relevant stability checks.

AHB Protocol